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b371ae0d4a
init_bsp_APIC() which works for the virtual wire mode is used in ISA irq initialization at boot time. With the new APIC interrupt delivery mode scheme, which initializes the APIC before the first interrupt is expected, init_bsp_APIC() is not longer required and can be removed. Signed-off-by: Dou Liyang <douly.fnst@cn.fujitsu.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: yinghai@kernel.org Cc: bhe@redhat.com Link: https://lkml.kernel.org/r/1505293975-26005-13-git-send-email-douly.fnst@cn.fujitsu.com
99 lines
2.4 KiB
C
99 lines
2.4 KiB
C
#include <linux/linkage.h>
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#include <linux/errno.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/ioport.h>
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#include <linux/interrupt.h>
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#include <linux/timex.h>
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#include <linux/random.h>
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#include <linux/kprobes.h>
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#include <linux/init.h>
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#include <linux/kernel_stat.h>
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#include <linux/device.h>
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#include <linux/bitops.h>
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#include <linux/acpi.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/atomic.h>
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#include <asm/timer.h>
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#include <asm/hw_irq.h>
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#include <asm/pgtable.h>
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#include <asm/desc.h>
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#include <asm/apic.h>
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#include <asm/setup.h>
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#include <asm/i8259.h>
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#include <asm/traps.h>
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#include <asm/prom.h>
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/*
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* ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
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* (these are usually mapped to vectors 0x30-0x3f)
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*/
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/*
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* The IO-APIC gives us many more interrupt sources. Most of these
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* are unused but an SMP system is supposed to have enough memory ...
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* sometimes (mostly wrt. hw bugs) we get corrupted vectors all
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* across the spectrum, so we really want to be prepared to get all
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* of these. Plus, more powerful systems might have more than 64
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* IO-APIC registers.
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*
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* (these are usually mapped into the 0x30-0xff vector range)
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*/
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/*
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* IRQ2 is cascade interrupt to second interrupt controller
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*/
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static struct irqaction irq2 = {
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.handler = no_action,
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.name = "cascade",
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.flags = IRQF_NO_THREAD,
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};
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DEFINE_PER_CPU(vector_irq_t, vector_irq) = {
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[0 ... NR_VECTORS - 1] = VECTOR_UNUSED,
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};
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void __init init_ISA_irqs(void)
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{
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struct irq_chip *chip = legacy_pic->chip;
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int i;
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legacy_pic->init(0);
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for (i = 0; i < nr_legacy_irqs(); i++)
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irq_set_chip_and_handler(i, chip, handle_level_irq);
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}
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void __init init_IRQ(void)
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{
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int i;
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/*
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* On cpu 0, Assign ISA_IRQ_VECTOR(irq) to IRQ 0..15.
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* If these IRQ's are handled by legacy interrupt-controllers like PIC,
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* then this configuration will likely be static after the boot. If
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* these IRQ's are handled by more mordern controllers like IO-APIC,
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* then this vector space can be freed and re-used dynamically as the
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* irq's migrate etc.
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*/
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for (i = 0; i < nr_legacy_irqs(); i++)
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per_cpu(vector_irq, 0)[ISA_IRQ_VECTOR(i)] = irq_to_desc(i);
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x86_init.irqs.intr_init();
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}
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void __init native_init_IRQ(void)
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{
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/* Execute any quirks before the call gates are initialised: */
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x86_init.irqs.pre_vector_init();
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idt_setup_apic_and_irq_gates();
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if (!acpi_ioapic && !of_ioapic && nr_legacy_irqs())
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setup_irq(2, &irq2);
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irq_ctx_init(smp_processor_id());
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}
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