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e321d02db8
The perf fuzzer caused Skylake machine to crash:
[ 9680.085831] Call Trace:
[ 9680.088301] <IRQ>
[ 9680.090363] perf_output_sample_regs+0x43/0xa0
[ 9680.094928] perf_output_sample+0x3aa/0x7a0
[ 9680.099181] perf_event_output_forward+0x53/0x80
[ 9680.103917] __perf_event_overflow+0x52/0xf0
[ 9680.108266] ? perf_trace_run_bpf_submit+0xc0/0xc0
[ 9680.113108] perf_swevent_hrtimer+0xe2/0x150
[ 9680.117475] ? check_preempt_wakeup+0x181/0x230
[ 9680.122091] ? check_preempt_curr+0x62/0x90
[ 9680.126361] ? ttwu_do_wakeup+0x19/0x140
[ 9680.130355] ? try_to_wake_up+0x54/0x460
[ 9680.134366] ? reweight_entity+0x15b/0x1a0
[ 9680.138559] ? __queue_work+0x103/0x3f0
[ 9680.142472] ? update_dl_rq_load_avg+0x1cd/0x270
[ 9680.147194] ? timerqueue_del+0x1e/0x40
[ 9680.151092] ? __remove_hrtimer+0x35/0x70
[ 9680.155191] __hrtimer_run_queues+0x100/0x280
[ 9680.159658] hrtimer_interrupt+0x100/0x220
[ 9680.163835] smp_apic_timer_interrupt+0x6a/0x140
[ 9680.168555] apic_timer_interrupt+0xf/0x20
[ 9680.172756] </IRQ>
The XMM registers can only be collected by PEBS hardware events on the
platforms with PEBS baseline support, e.g. Icelake, not software/probe
events.
Add capabilities flag PERF_PMU_CAP_EXTENDED_REGS to indicate the PMU
which support extended registers. For X86, the extended registers are
XMM registers.
Add has_extended_regs() to check if extended registers are applied.
The generic code define the mask of extended registers as 0 if arch
headers haven't overridden it.
Originally-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reported-by: Vince Weaver <vincent.weaver@maine.edu>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Fixes: 878068ea27 ("perf/x86: Support outputting XMM registers")
Link: https://lkml.kernel.org/r/1559081314-9714-1-git-send-email-kan.liang@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
59 lines
1.4 KiB
C
59 lines
1.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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#ifndef _ASM_X86_PERF_REGS_H
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#define _ASM_X86_PERF_REGS_H
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enum perf_event_x86_regs {
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PERF_REG_X86_AX,
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PERF_REG_X86_BX,
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PERF_REG_X86_CX,
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PERF_REG_X86_DX,
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PERF_REG_X86_SI,
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PERF_REG_X86_DI,
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PERF_REG_X86_BP,
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PERF_REG_X86_SP,
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PERF_REG_X86_IP,
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PERF_REG_X86_FLAGS,
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PERF_REG_X86_CS,
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PERF_REG_X86_SS,
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PERF_REG_X86_DS,
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PERF_REG_X86_ES,
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PERF_REG_X86_FS,
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PERF_REG_X86_GS,
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PERF_REG_X86_R8,
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PERF_REG_X86_R9,
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PERF_REG_X86_R10,
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PERF_REG_X86_R11,
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PERF_REG_X86_R12,
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PERF_REG_X86_R13,
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PERF_REG_X86_R14,
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PERF_REG_X86_R15,
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/* These are the limits for the GPRs. */
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PERF_REG_X86_32_MAX = PERF_REG_X86_GS + 1,
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PERF_REG_X86_64_MAX = PERF_REG_X86_R15 + 1,
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/* These all need two bits set because they are 128bit */
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PERF_REG_X86_XMM0 = 32,
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PERF_REG_X86_XMM1 = 34,
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PERF_REG_X86_XMM2 = 36,
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PERF_REG_X86_XMM3 = 38,
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PERF_REG_X86_XMM4 = 40,
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PERF_REG_X86_XMM5 = 42,
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PERF_REG_X86_XMM6 = 44,
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PERF_REG_X86_XMM7 = 46,
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PERF_REG_X86_XMM8 = 48,
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PERF_REG_X86_XMM9 = 50,
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PERF_REG_X86_XMM10 = 52,
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PERF_REG_X86_XMM11 = 54,
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PERF_REG_X86_XMM12 = 56,
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PERF_REG_X86_XMM13 = 58,
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PERF_REG_X86_XMM14 = 60,
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PERF_REG_X86_XMM15 = 62,
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/* These include both GPRs and XMMX registers */
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PERF_REG_X86_XMM_MAX = PERF_REG_X86_XMM15 + 2,
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};
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#define PERF_REG_EXTENDED_MASK (~((1ULL << PERF_REG_X86_XMM0) - 1))
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#endif /* _ASM_X86_PERF_REGS_H */
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