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For P4 model < 2, The MSR_FBC_REGISTER_ID ratio is undefined. Revert the commit that was added to handle that case, as it results in random MHz displayed. Something else will have to be done to properly handle model < 2. //commit 3e4159ab35c88aef5e063ba78796b277b762a30a //Author: matthias.christian <matthias.christian> //Date: Sat Feb 5 23:09:38 2005 +0000 // // [PATCH] speedstep-lib.c: fix frequency multiplier for Pentium4 models 0&1 // // The Pentium4 models 0&1 have a longer MSR_EBC_FREQUENCY_ID register as the // models 2&3, so the bit shift must be bigger. // // Signed-off-by: Matthias-Christian Ott <matthias.christian@tiscali.de> // Signed-off-by: Dominik Brodowski <linux@brodo.de> // Signed-off-by: Andrew Morton <akpm@osdl.org> // Signed-off-by: Linus Torvalds <torvalds@osdl.org> // // BKrev: 42055232eWM-NgjhZVir44mp5GXktQ http://bugzilla.kernel.org/show_bug.cgi?id=7186 Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
442 lines
11 KiB
C
442 lines
11 KiB
C
/*
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* (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
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*
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* Licensed under the terms of the GNU GPL License version 2.
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*
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* Library for common functions for Intel SpeedStep v.1 and v.2 support
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*
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* BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/init.h>
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#include <linux/cpufreq.h>
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#include <linux/slab.h>
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#include <asm/msr.h>
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#include "speedstep-lib.h"
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#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "speedstep-lib", msg)
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#ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK
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static int relaxed_check = 0;
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#else
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#define relaxed_check 0
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#endif
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/*********************************************************************
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* GET PROCESSOR CORE SPEED IN KHZ *
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*********************************************************************/
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static unsigned int pentium3_get_frequency (unsigned int processor)
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{
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/* See table 14 of p3_ds.pdf and table 22 of 29834003.pdf */
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struct {
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unsigned int ratio; /* Frequency Multiplier (x10) */
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u8 bitmap; /* power on configuration bits
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[27, 25:22] (in MSR 0x2a) */
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} msr_decode_mult [] = {
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{ 30, 0x01 },
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{ 35, 0x05 },
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{ 40, 0x02 },
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{ 45, 0x06 },
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{ 50, 0x00 },
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{ 55, 0x04 },
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{ 60, 0x0b },
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{ 65, 0x0f },
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{ 70, 0x09 },
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{ 75, 0x0d },
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{ 80, 0x0a },
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{ 85, 0x26 },
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{ 90, 0x20 },
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{ 100, 0x2b },
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{ 0, 0xff } /* error or unknown value */
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};
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/* PIII(-M) FSB settings: see table b1-b of 24547206.pdf */
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struct {
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unsigned int value; /* Front Side Bus speed in MHz */
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u8 bitmap; /* power on configuration bits [18: 19]
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(in MSR 0x2a) */
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} msr_decode_fsb [] = {
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{ 66, 0x0 },
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{ 100, 0x2 },
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{ 133, 0x1 },
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{ 0, 0xff}
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};
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u32 msr_lo, msr_tmp;
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int i = 0, j = 0;
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/* read MSR 0x2a - we only need the low 32 bits */
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rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
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dprintk("P3 - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
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msr_tmp = msr_lo;
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/* decode the FSB */
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msr_tmp &= 0x00c0000;
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msr_tmp >>= 18;
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while (msr_tmp != msr_decode_fsb[i].bitmap) {
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if (msr_decode_fsb[i].bitmap == 0xff)
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return 0;
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i++;
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}
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/* decode the multiplier */
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if (processor == SPEEDSTEP_PROCESSOR_PIII_C_EARLY) {
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dprintk("workaround for early PIIIs\n");
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msr_lo &= 0x03c00000;
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} else
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msr_lo &= 0x0bc00000;
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msr_lo >>= 22;
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while (msr_lo != msr_decode_mult[j].bitmap) {
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if (msr_decode_mult[j].bitmap == 0xff)
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return 0;
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j++;
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}
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dprintk("speed is %u\n", (msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100));
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return (msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100);
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}
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static unsigned int pentiumM_get_frequency(void)
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{
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u32 msr_lo, msr_tmp;
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rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
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dprintk("PM - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
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/* see table B-2 of 24547212.pdf */
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if (msr_lo & 0x00040000) {
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printk(KERN_DEBUG "speedstep-lib: PM - invalid FSB: 0x%x 0x%x\n", msr_lo, msr_tmp);
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return 0;
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}
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msr_tmp = (msr_lo >> 22) & 0x1f;
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dprintk("bits 22-26 are 0x%x, speed is %u\n", msr_tmp, (msr_tmp * 100 * 1000));
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return (msr_tmp * 100 * 1000);
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}
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static unsigned int pentium_core_get_frequency(void)
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{
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u32 fsb = 0;
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u32 msr_lo, msr_tmp;
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rdmsr(MSR_FSB_FREQ, msr_lo, msr_tmp);
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/* see table B-2 of 25366920.pdf */
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switch (msr_lo & 0x07) {
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case 5:
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fsb = 100000;
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break;
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case 1:
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fsb = 133333;
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break;
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case 3:
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fsb = 166667;
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break;
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default:
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printk(KERN_ERR "PCORE - MSR_FSB_FREQ undefined value");
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}
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rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
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dprintk("PCORE - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
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msr_tmp = (msr_lo >> 22) & 0x1f;
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dprintk("bits 22-26 are 0x%x, speed is %u\n", msr_tmp, (msr_tmp * fsb));
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return (msr_tmp * fsb);
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}
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static unsigned int pentium4_get_frequency(void)
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{
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struct cpuinfo_x86 *c = &boot_cpu_data;
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u32 msr_lo, msr_hi, mult;
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unsigned int fsb = 0;
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rdmsr(0x2c, msr_lo, msr_hi);
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dprintk("P4 - MSR_EBC_FREQUENCY_ID: 0x%x 0x%x\n", msr_lo, msr_hi);
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/* decode the FSB: see IA-32 Intel (C) Architecture Software
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* Developer's Manual, Volume 3: System Prgramming Guide,
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* revision #12 in Table B-1: MSRs in the Pentium 4 and
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* Intel Xeon Processors, on page B-4 and B-5.
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*/
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if (c->x86_model < 2)
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fsb = 100 * 1000;
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else {
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u8 fsb_code = (msr_lo >> 16) & 0x7;
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switch (fsb_code) {
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case 0:
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fsb = 100 * 1000;
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break;
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case 1:
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fsb = 13333 * 10;
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break;
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case 2:
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fsb = 200 * 1000;
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break;
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}
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}
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if (!fsb)
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printk(KERN_DEBUG "speedstep-lib: couldn't detect FSB speed. Please send an e-mail to <linux@brodo.de>\n");
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/* Multiplier. */
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mult = msr_lo >> 24;
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dprintk("P4 - FSB %u kHz; Multiplier %u; Speed %u kHz\n", fsb, mult, (fsb * mult));
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return (fsb * mult);
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}
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unsigned int speedstep_get_processor_frequency(unsigned int processor)
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{
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switch (processor) {
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case SPEEDSTEP_PROCESSOR_PCORE:
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return pentium_core_get_frequency();
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case SPEEDSTEP_PROCESSOR_PM:
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return pentiumM_get_frequency();
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case SPEEDSTEP_PROCESSOR_P4D:
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case SPEEDSTEP_PROCESSOR_P4M:
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return pentium4_get_frequency();
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case SPEEDSTEP_PROCESSOR_PIII_T:
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case SPEEDSTEP_PROCESSOR_PIII_C:
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case SPEEDSTEP_PROCESSOR_PIII_C_EARLY:
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return pentium3_get_frequency(processor);
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default:
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return 0;
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};
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return 0;
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}
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EXPORT_SYMBOL_GPL(speedstep_get_processor_frequency);
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/*********************************************************************
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* DETECT SPEEDSTEP-CAPABLE PROCESSOR *
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*********************************************************************/
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unsigned int speedstep_detect_processor (void)
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{
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struct cpuinfo_x86 *c = &cpu_data(0);
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u32 ebx, msr_lo, msr_hi;
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dprintk("x86: %x, model: %x\n", c->x86, c->x86_model);
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if ((c->x86_vendor != X86_VENDOR_INTEL) ||
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((c->x86 != 6) && (c->x86 != 0xF)))
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return 0;
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if (c->x86 == 0xF) {
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/* Intel Mobile Pentium 4-M
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* or Intel Mobile Pentium 4 with 533 MHz FSB */
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if (c->x86_model != 2)
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return 0;
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ebx = cpuid_ebx(0x00000001);
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ebx &= 0x000000FF;
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dprintk("ebx value is %x, x86_mask is %x\n", ebx, c->x86_mask);
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switch (c->x86_mask) {
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case 4:
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/*
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* B-stepping [M-P4-M]
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* sample has ebx = 0x0f, production has 0x0e.
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*/
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if ((ebx == 0x0e) || (ebx == 0x0f))
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return SPEEDSTEP_PROCESSOR_P4M;
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break;
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case 7:
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/*
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* C-stepping [M-P4-M]
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* needs to have ebx=0x0e, else it's a celeron:
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* cf. 25130917.pdf / page 7, footnote 5 even
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* though 25072120.pdf / page 7 doesn't say
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* samples are only of B-stepping...
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*/
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if (ebx == 0x0e)
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return SPEEDSTEP_PROCESSOR_P4M;
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break;
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case 9:
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/*
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* D-stepping [M-P4-M or M-P4/533]
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*
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* this is totally strange: CPUID 0x0F29 is
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* used by M-P4-M, M-P4/533 and(!) Celeron CPUs.
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* The latter need to be sorted out as they don't
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* support speedstep.
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* Celerons with CPUID 0x0F29 may have either
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* ebx=0x8 or 0xf -- 25130917.pdf doesn't say anything
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* specific.
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* M-P4-Ms may have either ebx=0xe or 0xf [see above]
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* M-P4/533 have either ebx=0xe or 0xf. [25317607.pdf]
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* also, M-P4M HTs have ebx=0x8, too
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* For now, they are distinguished by the model_id string
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*/
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if ((ebx == 0x0e) || (strstr(c->x86_model_id,"Mobile Intel(R) Pentium(R) 4") != NULL))
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return SPEEDSTEP_PROCESSOR_P4M;
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break;
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default:
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break;
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}
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return 0;
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}
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switch (c->x86_model) {
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case 0x0B: /* Intel PIII [Tualatin] */
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/* cpuid_ebx(1) is 0x04 for desktop PIII, 0x06 for mobile PIII-M */
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ebx = cpuid_ebx(0x00000001);
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dprintk("ebx is %x\n", ebx);
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ebx &= 0x000000FF;
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if (ebx != 0x06)
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return 0;
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/* So far all PIII-M processors support SpeedStep. See
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* Intel's 24540640.pdf of June 2003
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*/
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return SPEEDSTEP_PROCESSOR_PIII_T;
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case 0x08: /* Intel PIII [Coppermine] */
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/* all mobile PIII Coppermines have FSB 100 MHz
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* ==> sort out a few desktop PIIIs. */
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rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_hi);
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dprintk("Coppermine: MSR_IA32_EBL_CR_POWERON is 0x%x, 0x%x\n", msr_lo, msr_hi);
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msr_lo &= 0x00c0000;
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if (msr_lo != 0x0080000)
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return 0;
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/*
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* If the processor is a mobile version,
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* platform ID has bit 50 set
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* it has SpeedStep technology if either
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* bit 56 or 57 is set
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*/
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rdmsr(MSR_IA32_PLATFORM_ID, msr_lo, msr_hi);
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dprintk("Coppermine: MSR_IA32_PLATFORM ID is 0x%x, 0x%x\n", msr_lo, msr_hi);
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if ((msr_hi & (1<<18)) && (relaxed_check ? 1 : (msr_hi & (3<<24)))) {
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if (c->x86_mask == 0x01) {
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dprintk("early PIII version\n");
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return SPEEDSTEP_PROCESSOR_PIII_C_EARLY;
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} else
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return SPEEDSTEP_PROCESSOR_PIII_C;
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}
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default:
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return 0;
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}
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}
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EXPORT_SYMBOL_GPL(speedstep_detect_processor);
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/*********************************************************************
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* DETECT SPEEDSTEP SPEEDS *
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*********************************************************************/
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unsigned int speedstep_get_freqs(unsigned int processor,
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unsigned int *low_speed,
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unsigned int *high_speed,
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unsigned int *transition_latency,
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void (*set_state) (unsigned int state))
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{
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unsigned int prev_speed;
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unsigned int ret = 0;
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unsigned long flags;
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struct timeval tv1, tv2;
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if ((!processor) || (!low_speed) || (!high_speed) || (!set_state))
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return -EINVAL;
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dprintk("trying to determine both speeds\n");
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/* get current speed */
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prev_speed = speedstep_get_processor_frequency(processor);
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if (!prev_speed)
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return -EIO;
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dprintk("previous speed is %u\n", prev_speed);
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local_irq_save(flags);
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/* switch to low state */
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set_state(SPEEDSTEP_LOW);
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*low_speed = speedstep_get_processor_frequency(processor);
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if (!*low_speed) {
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ret = -EIO;
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goto out;
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}
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dprintk("low speed is %u\n", *low_speed);
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/* start latency measurement */
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if (transition_latency)
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do_gettimeofday(&tv1);
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/* switch to high state */
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set_state(SPEEDSTEP_HIGH);
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/* end latency measurement */
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if (transition_latency)
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do_gettimeofday(&tv2);
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*high_speed = speedstep_get_processor_frequency(processor);
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if (!*high_speed) {
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ret = -EIO;
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goto out;
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}
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dprintk("high speed is %u\n", *high_speed);
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if (*low_speed == *high_speed) {
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ret = -ENODEV;
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goto out;
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}
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/* switch to previous state, if necessary */
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if (*high_speed != prev_speed)
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set_state(SPEEDSTEP_LOW);
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if (transition_latency) {
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*transition_latency = (tv2.tv_sec - tv1.tv_sec) * USEC_PER_SEC +
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tv2.tv_usec - tv1.tv_usec;
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dprintk("transition latency is %u uSec\n", *transition_latency);
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/* convert uSec to nSec and add 20% for safety reasons */
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*transition_latency *= 1200;
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/* check if the latency measurement is too high or too low
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* and set it to a safe value (500uSec) in that case
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*/
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if (*transition_latency > 10000000 || *transition_latency < 50000) {
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printk (KERN_WARNING "speedstep: frequency transition measured seems out of "
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"range (%u nSec), falling back to a safe one of %u nSec.\n",
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*transition_latency, 500000);
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*transition_latency = 500000;
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}
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}
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out:
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local_irq_restore(flags);
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return (ret);
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}
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EXPORT_SYMBOL_GPL(speedstep_get_freqs);
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#ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK
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module_param(relaxed_check, int, 0444);
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MODULE_PARM_DESC(relaxed_check, "Don't do all checks for speedstep capability.");
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#endif
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MODULE_AUTHOR ("Dominik Brodowski <linux@brodo.de>");
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MODULE_DESCRIPTION ("Library for Intel SpeedStep 1 or 2 cpufreq drivers.");
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MODULE_LICENSE ("GPL");
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