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While platform firmware takes some responsibility for mapping the RAM capacity of CXL devices present at boot, the OS is responsible for mapping the remainder and hot-added devices. Platform firmware is also responsible for identifying the platform general purpose memory pool, typically DDR attached DRAM, and arranging for the remainder to be 'Soft Reserved'. That reservation allows the CXL subsystem to route the memory to core-mm via memory-hotplug (dax_kmem), or leave it for dedicated access (device-dax). The new 'struct cxl_dax_region' object allows for a CXL memory resource (region) to be published, but also allow for udev and module policy to act on that event. It also prevents cxl_core.ko from having a module loading dependency on any drivers/dax/ modules. Tested-by: Fan Ni <fan.ni@samsung.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/167602003896.1924368.10335442077318970468.stgit@dwillia2-xfh.jf.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
68 lines
2.3 KiB
C
68 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright(c) 2020 Intel Corporation. */
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#ifndef __CXL_CORE_H__
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#define __CXL_CORE_H__
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extern const struct device_type cxl_nvdimm_bridge_type;
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extern const struct device_type cxl_nvdimm_type;
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extern struct attribute_group cxl_base_attribute_group;
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#ifdef CONFIG_CXL_REGION
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extern struct device_attribute dev_attr_create_pmem_region;
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extern struct device_attribute dev_attr_create_ram_region;
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extern struct device_attribute dev_attr_delete_region;
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extern struct device_attribute dev_attr_region;
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extern const struct device_type cxl_pmem_region_type;
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extern const struct device_type cxl_dax_region_type;
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extern const struct device_type cxl_region_type;
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void cxl_decoder_kill_region(struct cxl_endpoint_decoder *cxled);
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#define CXL_REGION_ATTR(x) (&dev_attr_##x.attr)
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#define CXL_REGION_TYPE(x) (&cxl_region_type)
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#define SET_CXL_REGION_ATTR(x) (&dev_attr_##x.attr),
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#define CXL_PMEM_REGION_TYPE(x) (&cxl_pmem_region_type)
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#define CXL_DAX_REGION_TYPE(x) (&cxl_dax_region_type)
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int cxl_region_init(void);
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void cxl_region_exit(void);
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#else
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static inline void cxl_decoder_kill_region(struct cxl_endpoint_decoder *cxled)
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{
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}
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static inline int cxl_region_init(void)
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{
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return 0;
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}
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static inline void cxl_region_exit(void)
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{
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}
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#define CXL_REGION_ATTR(x) NULL
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#define CXL_REGION_TYPE(x) NULL
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#define SET_CXL_REGION_ATTR(x)
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#define CXL_PMEM_REGION_TYPE(x) NULL
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#define CXL_DAX_REGION_TYPE(x) NULL
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#endif
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struct cxl_send_command;
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struct cxl_mem_query_commands;
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int cxl_query_cmd(struct cxl_memdev *cxlmd,
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struct cxl_mem_query_commands __user *q);
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int cxl_send_cmd(struct cxl_memdev *cxlmd, struct cxl_send_command __user *s);
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void __iomem *devm_cxl_iomap_block(struct device *dev, resource_size_t addr,
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resource_size_t length);
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struct dentry *cxl_debugfs_create_dir(const char *dir);
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int cxl_dpa_set_mode(struct cxl_endpoint_decoder *cxled,
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enum cxl_decoder_mode mode);
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int cxl_dpa_alloc(struct cxl_endpoint_decoder *cxled, unsigned long long size);
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int cxl_dpa_free(struct cxl_endpoint_decoder *cxled);
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resource_size_t cxl_dpa_size(struct cxl_endpoint_decoder *cxled);
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resource_size_t cxl_dpa_resource_start(struct cxl_endpoint_decoder *cxled);
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extern struct rw_semaphore cxl_dpa_rwsem;
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int cxl_memdev_init(void);
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void cxl_memdev_exit(void);
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void cxl_mbox_init(void);
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#endif /* __CXL_CORE_H__ */
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