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b243b77c70
Make sure we are in a know good state at end of probe : Reset FIFO logic and registers, and make sure REC and RPL functions along with FIFO service are disabled (SACR0_RST enables REC and RPL). Resetting loses current settings so remove reset from stream startup. Now reset occurs only at probe. Signed-off-by: Karl Beldan <karl.beldan@mobile-devices.fr> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> |
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| atmel | ||
| au1x | ||
| blackfin | ||
| codecs | ||
| davinci | ||
| fsl | ||
| omap | ||
| pxa | ||
| s3c24xx | ||
| s6000 | ||
| sh | ||
| Kconfig | ||
| Makefile | ||
| soc-core.c | ||
| soc-dapm.c | ||
| soc-jack.c | ||