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b1f156db47
The imx6q clock driver currently hard-codes all PLL clocks to source from OSC24M without BYPASS support. The patch adds the missing lvds_in clock which is mutually exclusive with lvds_gate, and implements BYPASS and BYPASS_CLK_SRC selection for PLL clocks as per Figure 10-3. Primary Clock Generation in IMX6DQRM, i.e. both BYPASS_CLK_SRC and BYPASS bits are implemented as mux clocks, and ENABLE bit of PLL clocks is implemented as a gate clock after BYPASS mux. Signed-off-by: Shawn Guo <shawn.guo@freescale.com> |
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clk | ||
clock | ||
dma | ||
gpio | ||
input | ||
interrupt-controller | ||
mfd | ||
phy | ||
pinctrl | ||
pwm | ||
reset | ||
reset-controller | ||
soc | ||
sound | ||
spmi | ||
thermal |