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b1dc3c4820
There is no need for keeping separate pmu structs. We can enable
amd_{get,put}_event_constraints() functions also for family 15h event.
The advantage is that there is only a single pmu struct for all AMD
cpus. This patch introduces functions to setup the pmu to enabe core
performance counters or counter constraints.
Also, cpuid checks are used instead of family checks where
possible. Thus, it enables the code independently of cpu families if
the feature flag is set.
Signed-off-by: Robert Richter <robert.richter@amd.com>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/r/1340217996-2254-4-git-send-email-robert.richter@amd.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
259 lines
7.0 KiB
C
259 lines
7.0 KiB
C
#ifndef _ASM_X86_PERF_EVENT_H
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#define _ASM_X86_PERF_EVENT_H
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/*
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* Performance event hw details:
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*/
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#define INTEL_PMC_MAX_GENERIC 32
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#define INTEL_PMC_MAX_FIXED 3
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#define INTEL_PMC_IDX_FIXED 32
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#define X86_PMC_IDX_MAX 64
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#define MSR_ARCH_PERFMON_PERFCTR0 0xc1
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#define MSR_ARCH_PERFMON_PERFCTR1 0xc2
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#define MSR_ARCH_PERFMON_EVENTSEL0 0x186
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#define MSR_ARCH_PERFMON_EVENTSEL1 0x187
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#define ARCH_PERFMON_EVENTSEL_EVENT 0x000000FFULL
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#define ARCH_PERFMON_EVENTSEL_UMASK 0x0000FF00ULL
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#define ARCH_PERFMON_EVENTSEL_USR (1ULL << 16)
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#define ARCH_PERFMON_EVENTSEL_OS (1ULL << 17)
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#define ARCH_PERFMON_EVENTSEL_EDGE (1ULL << 18)
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#define ARCH_PERFMON_EVENTSEL_PIN_CONTROL (1ULL << 19)
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#define ARCH_PERFMON_EVENTSEL_INT (1ULL << 20)
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#define ARCH_PERFMON_EVENTSEL_ANY (1ULL << 21)
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#define ARCH_PERFMON_EVENTSEL_ENABLE (1ULL << 22)
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#define ARCH_PERFMON_EVENTSEL_INV (1ULL << 23)
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#define ARCH_PERFMON_EVENTSEL_CMASK 0xFF000000ULL
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#define AMD_PERFMON_EVENTSEL_GUESTONLY (1ULL << 40)
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#define AMD_PERFMON_EVENTSEL_HOSTONLY (1ULL << 41)
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#define AMD64_EVENTSEL_EVENT \
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(ARCH_PERFMON_EVENTSEL_EVENT | (0x0FULL << 32))
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#define INTEL_ARCH_EVENT_MASK \
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(ARCH_PERFMON_EVENTSEL_UMASK | ARCH_PERFMON_EVENTSEL_EVENT)
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#define X86_RAW_EVENT_MASK \
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(ARCH_PERFMON_EVENTSEL_EVENT | \
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ARCH_PERFMON_EVENTSEL_UMASK | \
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ARCH_PERFMON_EVENTSEL_EDGE | \
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ARCH_PERFMON_EVENTSEL_INV | \
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ARCH_PERFMON_EVENTSEL_CMASK)
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#define AMD64_RAW_EVENT_MASK \
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(X86_RAW_EVENT_MASK | \
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AMD64_EVENTSEL_EVENT)
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#define AMD64_NUM_COUNTERS 4
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#define AMD64_NUM_COUNTERS_CORE 6
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#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL 0x3c
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#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK (0x00 << 8)
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#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX 0
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#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \
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(1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX))
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#define ARCH_PERFMON_BRANCH_MISSES_RETIRED 6
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#define ARCH_PERFMON_EVENTS_COUNT 7
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/*
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* Intel "Architectural Performance Monitoring" CPUID
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* detection/enumeration details:
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*/
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union cpuid10_eax {
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struct {
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unsigned int version_id:8;
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unsigned int num_counters:8;
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unsigned int bit_width:8;
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unsigned int mask_length:8;
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} split;
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unsigned int full;
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};
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union cpuid10_ebx {
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struct {
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unsigned int no_unhalted_core_cycles:1;
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unsigned int no_instructions_retired:1;
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unsigned int no_unhalted_reference_cycles:1;
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unsigned int no_llc_reference:1;
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unsigned int no_llc_misses:1;
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unsigned int no_branch_instruction_retired:1;
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unsigned int no_branch_misses_retired:1;
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} split;
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unsigned int full;
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};
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union cpuid10_edx {
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struct {
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unsigned int num_counters_fixed:5;
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unsigned int bit_width_fixed:8;
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unsigned int reserved:19;
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} split;
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unsigned int full;
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};
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struct x86_pmu_capability {
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int version;
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int num_counters_gp;
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int num_counters_fixed;
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int bit_width_gp;
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int bit_width_fixed;
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unsigned int events_mask;
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int events_mask_len;
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};
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/*
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* Fixed-purpose performance events:
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*/
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/*
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* All 3 fixed-mode PMCs are configured via this single MSR:
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*/
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#define MSR_ARCH_PERFMON_FIXED_CTR_CTRL 0x38d
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/*
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* The counts are available in three separate MSRs:
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*/
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/* Instr_Retired.Any: */
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#define MSR_ARCH_PERFMON_FIXED_CTR0 0x309
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#define INTEL_PMC_IDX_FIXED_INSTRUCTIONS (INTEL_PMC_IDX_FIXED + 0)
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/* CPU_CLK_Unhalted.Core: */
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#define MSR_ARCH_PERFMON_FIXED_CTR1 0x30a
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#define INTEL_PMC_IDX_FIXED_CPU_CYCLES (INTEL_PMC_IDX_FIXED + 1)
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/* CPU_CLK_Unhalted.Ref: */
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#define MSR_ARCH_PERFMON_FIXED_CTR2 0x30b
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#define INTEL_PMC_IDX_FIXED_REF_CYCLES (INTEL_PMC_IDX_FIXED + 2)
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#define INTEL_PMC_MSK_FIXED_REF_CYCLES (1ULL << INTEL_PMC_IDX_FIXED_REF_CYCLES)
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/*
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* We model BTS tracing as another fixed-mode PMC.
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*
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* We choose a value in the middle of the fixed event range, since lower
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* values are used by actual fixed events and higher values are used
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* to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr.
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*/
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#define INTEL_PMC_IDX_FIXED_BTS (INTEL_PMC_IDX_FIXED + 16)
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/*
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* IBS cpuid feature detection
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*/
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#define IBS_CPUID_FEATURES 0x8000001b
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/*
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* Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but
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* bit 0 is used to indicate the existence of IBS.
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*/
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#define IBS_CAPS_AVAIL (1U<<0)
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#define IBS_CAPS_FETCHSAM (1U<<1)
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#define IBS_CAPS_OPSAM (1U<<2)
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#define IBS_CAPS_RDWROPCNT (1U<<3)
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#define IBS_CAPS_OPCNT (1U<<4)
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#define IBS_CAPS_BRNTRGT (1U<<5)
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#define IBS_CAPS_OPCNTEXT (1U<<6)
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#define IBS_CAPS_RIPINVALIDCHK (1U<<7)
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#define IBS_CAPS_DEFAULT (IBS_CAPS_AVAIL \
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| IBS_CAPS_FETCHSAM \
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| IBS_CAPS_OPSAM)
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/*
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* IBS APIC setup
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*/
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#define IBSCTL 0x1cc
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#define IBSCTL_LVT_OFFSET_VALID (1ULL<<8)
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#define IBSCTL_LVT_OFFSET_MASK 0x0F
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/* ibs fetch bits/masks */
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#define IBS_FETCH_RAND_EN (1ULL<<57)
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#define IBS_FETCH_VAL (1ULL<<49)
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#define IBS_FETCH_ENABLE (1ULL<<48)
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#define IBS_FETCH_CNT 0xFFFF0000ULL
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#define IBS_FETCH_MAX_CNT 0x0000FFFFULL
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/* ibs op bits/masks */
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/* lower 4 bits of the current count are ignored: */
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#define IBS_OP_CUR_CNT (0xFFFF0ULL<<32)
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#define IBS_OP_CNT_CTL (1ULL<<19)
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#define IBS_OP_VAL (1ULL<<18)
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#define IBS_OP_ENABLE (1ULL<<17)
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#define IBS_OP_MAX_CNT 0x0000FFFFULL
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#define IBS_OP_MAX_CNT_EXT 0x007FFFFFULL /* not a register bit mask */
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#define IBS_RIP_INVALID (1ULL<<38)
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#ifdef CONFIG_X86_LOCAL_APIC
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extern u32 get_ibs_caps(void);
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#else
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static inline u32 get_ibs_caps(void) { return 0; }
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#endif
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#ifdef CONFIG_PERF_EVENTS
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extern void perf_events_lapic_init(void);
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/*
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* Abuse bit 3 of the cpu eflags register to indicate proper PEBS IP fixups.
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* This flag is otherwise unused and ABI specified to be 0, so nobody should
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* care what we do with it.
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*/
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#define PERF_EFLAGS_EXACT (1UL << 3)
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struct pt_regs;
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extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
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extern unsigned long perf_misc_flags(struct pt_regs *regs);
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#define perf_misc_flags(regs) perf_misc_flags(regs)
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#include <asm/stacktrace.h>
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/*
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* We abuse bit 3 from flags to pass exact information, see perf_misc_flags
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* and the comment with PERF_EFLAGS_EXACT.
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*/
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#define perf_arch_fetch_caller_regs(regs, __ip) { \
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(regs)->ip = (__ip); \
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(regs)->bp = caller_frame_pointer(); \
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(regs)->cs = __KERNEL_CS; \
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regs->flags = 0; \
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asm volatile( \
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_ASM_MOV "%%"_ASM_SP ", %0\n" \
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: "=m" ((regs)->sp) \
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:: "memory" \
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); \
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}
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struct perf_guest_switch_msr {
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unsigned msr;
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u64 host, guest;
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};
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extern struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr);
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extern void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap);
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#else
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static inline perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
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{
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*nr = 0;
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return NULL;
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}
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static inline void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
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{
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memset(cap, 0, sizeof(*cap));
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}
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static inline void perf_events_lapic_init(void) { }
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#endif
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#if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD)
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extern void amd_pmu_enable_virt(void);
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extern void amd_pmu_disable_virt(void);
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#else
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static inline void amd_pmu_enable_virt(void) { }
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static inline void amd_pmu_disable_virt(void) { }
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#endif
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#endif /* _ASM_X86_PERF_EVENT_H */
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