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cb678d6016
When we detect support for 16bit VMID in ID_AA64MMFR1, we set the VTCR_EL2_VS field to 1 to make use of 16bit vmids. But, with commit3a3604bc5e("arm64: KVM: Switch to C-based stage2 init") this is broken and we corrupt VTCR_EL2:T0SZ instead of updating the VS field. VTCR_EL2_VS was actually defined to the field shift (19) and not the real value for VS. This patch fixes the issue. Fixes: commit3a3604bc5e("arm64: KVM: Switch to C-based stage2 init") Cc: Christoffer Dall <christoffer.dall@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
269 lines
7.8 KiB
C
269 lines
7.8 KiB
C
/*
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* Macros for accessing system registers with older binutils.
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*
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* Copyright (C) 2014 ARM Ltd.
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* Author: Catalin Marinas <catalin.marinas@arm.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_SYSREG_H
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#define __ASM_SYSREG_H
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#include <linux/stringify.h>
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#include <asm/opcodes.h>
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/*
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* ARMv8 ARM reserves the following encoding for system registers:
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* (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
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* C5.2, version:ARM DDI 0487A.f)
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* [20-19] : Op0
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* [18-16] : Op1
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* [15-12] : CRn
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* [11-8] : CRm
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* [7-5] : Op2
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*/
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#define sys_reg(op0, op1, crn, crm, op2) \
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((((op0)&3)<<19)|((op1)<<16)|((crn)<<12)|((crm)<<8)|((op2)<<5))
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#define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
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#define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
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#define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
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#define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1, 0)
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#define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1)
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#define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2)
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#define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1, 4)
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#define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5)
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#define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6)
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#define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7)
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#define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0)
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#define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1)
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#define SYS_ID_ISAR2_EL1 sys_reg(3, 0, 0, 2, 2)
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#define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3)
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#define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4)
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#define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5)
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#define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6)
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#define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0)
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#define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1)
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#define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2)
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#define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0)
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#define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1)
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#define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0)
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#define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1)
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#define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0)
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#define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1)
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#define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0)
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#define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1)
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#define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2)
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#define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0)
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#define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1)
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#define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7)
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#define REG_PSTATE_PAN_IMM sys_reg(0, 0, 4, 0, 4)
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#define REG_PSTATE_UAO_IMM sys_reg(0, 0, 4, 0, 3)
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#define SET_PSTATE_PAN(x) __inst_arm(0xd5000000 | REG_PSTATE_PAN_IMM |\
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(!!x)<<8 | 0x1f)
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#define SET_PSTATE_UAO(x) __inst_arm(0xd5000000 | REG_PSTATE_UAO_IMM |\
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(!!x)<<8 | 0x1f)
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/* SCTLR_EL1 */
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#define SCTLR_EL1_CP15BEN (0x1 << 5)
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#define SCTLR_EL1_SED (0x1 << 8)
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#define SCTLR_EL1_SPAN (0x1 << 23)
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/* id_aa64isar0 */
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#define ID_AA64ISAR0_RDM_SHIFT 28
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#define ID_AA64ISAR0_ATOMICS_SHIFT 20
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#define ID_AA64ISAR0_CRC32_SHIFT 16
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#define ID_AA64ISAR0_SHA2_SHIFT 12
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#define ID_AA64ISAR0_SHA1_SHIFT 8
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#define ID_AA64ISAR0_AES_SHIFT 4
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/* id_aa64pfr0 */
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#define ID_AA64PFR0_GIC_SHIFT 24
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#define ID_AA64PFR0_ASIMD_SHIFT 20
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#define ID_AA64PFR0_FP_SHIFT 16
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#define ID_AA64PFR0_EL3_SHIFT 12
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#define ID_AA64PFR0_EL2_SHIFT 8
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#define ID_AA64PFR0_EL1_SHIFT 4
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#define ID_AA64PFR0_EL0_SHIFT 0
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#define ID_AA64PFR0_FP_NI 0xf
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#define ID_AA64PFR0_FP_SUPPORTED 0x0
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#define ID_AA64PFR0_ASIMD_NI 0xf
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#define ID_AA64PFR0_ASIMD_SUPPORTED 0x0
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#define ID_AA64PFR0_EL1_64BIT_ONLY 0x1
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#define ID_AA64PFR0_EL0_64BIT_ONLY 0x1
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/* id_aa64mmfr0 */
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#define ID_AA64MMFR0_TGRAN4_SHIFT 28
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#define ID_AA64MMFR0_TGRAN64_SHIFT 24
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#define ID_AA64MMFR0_TGRAN16_SHIFT 20
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#define ID_AA64MMFR0_BIGENDEL0_SHIFT 16
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#define ID_AA64MMFR0_SNSMEM_SHIFT 12
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#define ID_AA64MMFR0_BIGENDEL_SHIFT 8
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#define ID_AA64MMFR0_ASID_SHIFT 4
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#define ID_AA64MMFR0_PARANGE_SHIFT 0
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#define ID_AA64MMFR0_TGRAN4_NI 0xf
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#define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0
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#define ID_AA64MMFR0_TGRAN64_NI 0xf
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#define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0
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#define ID_AA64MMFR0_TGRAN16_NI 0x0
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#define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1
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/* id_aa64mmfr1 */
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#define ID_AA64MMFR1_PAN_SHIFT 20
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#define ID_AA64MMFR1_LOR_SHIFT 16
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#define ID_AA64MMFR1_HPD_SHIFT 12
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#define ID_AA64MMFR1_VHE_SHIFT 8
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#define ID_AA64MMFR1_VMIDBITS_SHIFT 4
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#define ID_AA64MMFR1_HADBS_SHIFT 0
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#define ID_AA64MMFR1_VMIDBITS_8 0
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#define ID_AA64MMFR1_VMIDBITS_16 2
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/* id_aa64mmfr2 */
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#define ID_AA64MMFR2_UAO_SHIFT 4
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/* id_aa64dfr0 */
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#define ID_AA64DFR0_CTX_CMPS_SHIFT 28
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#define ID_AA64DFR0_WRPS_SHIFT 20
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#define ID_AA64DFR0_BRPS_SHIFT 12
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#define ID_AA64DFR0_PMUVER_SHIFT 8
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#define ID_AA64DFR0_TRACEVER_SHIFT 4
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#define ID_AA64DFR0_DEBUGVER_SHIFT 0
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#define ID_ISAR5_RDM_SHIFT 24
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#define ID_ISAR5_CRC32_SHIFT 16
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#define ID_ISAR5_SHA2_SHIFT 12
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#define ID_ISAR5_SHA1_SHIFT 8
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#define ID_ISAR5_AES_SHIFT 4
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#define ID_ISAR5_SEVL_SHIFT 0
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#define MVFR0_FPROUND_SHIFT 28
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#define MVFR0_FPSHVEC_SHIFT 24
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#define MVFR0_FPSQRT_SHIFT 20
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#define MVFR0_FPDIVIDE_SHIFT 16
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#define MVFR0_FPTRAP_SHIFT 12
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#define MVFR0_FPDP_SHIFT 8
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#define MVFR0_FPSP_SHIFT 4
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#define MVFR0_SIMD_SHIFT 0
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#define MVFR1_SIMDFMAC_SHIFT 28
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#define MVFR1_FPHP_SHIFT 24
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#define MVFR1_SIMDHP_SHIFT 20
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#define MVFR1_SIMDSP_SHIFT 16
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#define MVFR1_SIMDINT_SHIFT 12
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#define MVFR1_SIMDLS_SHIFT 8
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#define MVFR1_FPDNAN_SHIFT 4
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#define MVFR1_FPFTZ_SHIFT 0
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#define ID_AA64MMFR0_TGRAN4_SHIFT 28
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#define ID_AA64MMFR0_TGRAN64_SHIFT 24
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#define ID_AA64MMFR0_TGRAN16_SHIFT 20
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#define ID_AA64MMFR0_TGRAN4_NI 0xf
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#define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0
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#define ID_AA64MMFR0_TGRAN64_NI 0xf
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#define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0
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#define ID_AA64MMFR0_TGRAN16_NI 0x0
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#define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1
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#if defined(CONFIG_ARM64_4K_PAGES)
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#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT
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#define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN4_SUPPORTED
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#elif defined(CONFIG_ARM64_16K_PAGES)
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#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN16_SHIFT
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#define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN16_SUPPORTED
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#elif defined(CONFIG_ARM64_64K_PAGES)
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#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN64_SHIFT
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#define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN64_SUPPORTED
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#endif
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#ifdef __ASSEMBLY__
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.irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
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.equ .L__reg_num_x\num, \num
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.endr
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.equ .L__reg_num_xzr, 31
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.macro mrs_s, rt, sreg
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.inst 0xd5200000|(\sreg)|(.L__reg_num_\rt)
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.endm
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.macro msr_s, sreg, rt
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.inst 0xd5000000|(\sreg)|(.L__reg_num_\rt)
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.endm
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#else
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#include <linux/types.h>
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asm(
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" .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n"
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" .equ .L__reg_num_x\\num, \\num\n"
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" .endr\n"
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" .equ .L__reg_num_xzr, 31\n"
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"\n"
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" .macro mrs_s, rt, sreg\n"
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" .inst 0xd5200000|(\\sreg)|(.L__reg_num_\\rt)\n"
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" .endm\n"
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"\n"
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" .macro msr_s, sreg, rt\n"
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" .inst 0xd5000000|(\\sreg)|(.L__reg_num_\\rt)\n"
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" .endm\n"
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);
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static inline void config_sctlr_el1(u32 clear, u32 set)
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{
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u32 val;
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asm volatile("mrs %0, sctlr_el1" : "=r" (val));
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val &= ~clear;
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val |= set;
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asm volatile("msr sctlr_el1, %0" : : "r" (val));
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}
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/*
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* Unlike read_cpuid, calls to read_sysreg are never expected to be
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* optimized away or replaced with synthetic values.
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*/
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#define read_sysreg(r) ({ \
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u64 __val; \
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asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \
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__val; \
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})
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#define write_sysreg(v, r) do { \
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u64 __val = (u64)v; \
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asm volatile("msr " __stringify(r) ", %0" \
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: : "r" (__val)); \
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} while (0)
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#endif
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#endif /* __ASM_SYSREG_H */
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