mirror of
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3efa7f1feb
- Fix Tegra OF node reference leak (Nishka Dasgupta)
- Add #defines for PCIe Data Link Feature and Physical Layer 16.0 GT/s
features (Vidya Sagar)
- Disable MSI for Tegra Root Ports since they don't support using MSI for
all Root Port events (Vidya Sagar)
- Group DesignWare write-protected register writes together (Vidya Sagar)
- Move DesignWare capability search interfaces so they can be used by
both host and endpoint drivers (Vidya Sagar)
- Add DesignWare extended capability search interfaces (Vidya Sagar)
- Export dw_pcie_wait_for_link() so drivers can be modules (Vidya Sagar)
- Add "snps,enable-cdm-check" DT binding for Configuration Dependent
Module (CDM) register checking (Vidya Sagar)
- Add DesignWare support for "snps,enable-cdm-check" CDM checking (Vidya
Sagar)
- Add "supports-clkreq" DT binding for host drivers to decide whether to
advertise low power features (Vidya Sagar)
- Add DT binding for Tegra194 (Vidya Sagar)
- Add DT binding for Tegra194 P2U (PIPE to UPHY) block (Vidya Sagar)
- Add support for Tegra194 P2U (PIPE to UPHY) (Vidya Sagar)
- Add support for Tegra194 host controller (Vidya Sagar)
- Add Tegra support for sideband PERST# and CLKREQ# for C5 (Vidya Sagar)
- Add Tegra support for slot regulators for p2972-0000 platform (Vidya
Sagar)
* lorenzo/pci/tegra:
arm64: tegra: Add PCIe slot supply information in p2972-0000 platform
arm64: tegra: Add configuration for PCIe C5 sideband signals
PCI: tegra: Add support to enable slot regulators
PCI: tegra: Add support to configure sideband pins
dt-bindings: PCI: tegra: Add PCIe slot supplies regulator entries
dt-bindings: PCI: tegra: Add sideband pins configuration entries
PCI: tegra: Add Tegra194 PCIe support
phy: tegra: Add PCIe PIPE2UPHY support
dt-bindings: PHY: P2U: Add Tegra194 P2U block
dt-bindings: PCI: tegra: Add device tree support for Tegra194
dt-bindings: Add PCIe supports-clkreq property
PCI: dwc: Add support to enable CDM register check
dt-bindings: PCI: designware: Add binding for CDM register check
PCI: dwc: Export dw_pcie_wait_for_link() API
PCI: dwc: Add extended configuration space capability search API
PCI: dwc: Move config space capability search API
PCI: dwc: Group DBI registers writes requiring unlocking
PCI: Disable MSI for Tegra root ports
PCI: Add #defines for some of PCIe spec r4.0 features
PCI: tegra: Fix OF node reference leak
272 lines
8.5 KiB
Plaintext
272 lines
8.5 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0
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menu "DesignWare PCI Core Support"
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depends on PCI
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config PCIE_DW
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bool
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config PCIE_DW_HOST
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bool
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depends on PCI_MSI_IRQ_DOMAIN
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select PCIE_DW
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config PCIE_DW_EP
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bool
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depends on PCI_ENDPOINT
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select PCIE_DW
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config PCI_DRA7XX
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bool
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config PCI_DRA7XX_HOST
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bool "TI DRA7xx PCIe controller Host Mode"
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depends on SOC_DRA7XX || COMPILE_TEST
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depends on PCI_MSI_IRQ_DOMAIN
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depends on OF && HAS_IOMEM && TI_PIPE3
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select PCIE_DW_HOST
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select PCI_DRA7XX
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default y
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help
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Enables support for the PCIe controller in the DRA7xx SoC to work in
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host mode. There are two instances of PCIe controller in DRA7xx.
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This controller can work either as EP or RC. In order to enable
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host-specific features PCI_DRA7XX_HOST must be selected and in order
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to enable device-specific features PCI_DRA7XX_EP must be selected.
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This uses the DesignWare core.
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config PCI_DRA7XX_EP
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bool "TI DRA7xx PCIe controller Endpoint Mode"
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depends on SOC_DRA7XX || COMPILE_TEST
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depends on PCI_ENDPOINT
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depends on OF && HAS_IOMEM && TI_PIPE3
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select PCIE_DW_EP
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select PCI_DRA7XX
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help
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Enables support for the PCIe controller in the DRA7xx SoC to work in
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endpoint mode. There are two instances of PCIe controller in DRA7xx.
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This controller can work either as EP or RC. In order to enable
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host-specific features PCI_DRA7XX_HOST must be selected and in order
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to enable device-specific features PCI_DRA7XX_EP must be selected.
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This uses the DesignWare core.
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config PCIE_DW_PLAT
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bool
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config PCIE_DW_PLAT_HOST
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bool "Platform bus based DesignWare PCIe Controller - Host mode"
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depends on PCI && PCI_MSI_IRQ_DOMAIN
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select PCIE_DW_HOST
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select PCIE_DW_PLAT
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help
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Enables support for the PCIe controller in the Designware IP to
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work in host mode. There are two instances of PCIe controller in
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Designware IP.
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This controller can work either as EP or RC. In order to enable
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host-specific features PCIE_DW_PLAT_HOST must be selected and in
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order to enable device-specific features PCI_DW_PLAT_EP must be
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selected.
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config PCIE_DW_PLAT_EP
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bool "Platform bus based DesignWare PCIe Controller - Endpoint mode"
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depends on PCI && PCI_MSI_IRQ_DOMAIN
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depends on PCI_ENDPOINT
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select PCIE_DW_EP
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select PCIE_DW_PLAT
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help
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Enables support for the PCIe controller in the Designware IP to
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work in endpoint mode. There are two instances of PCIe controller
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in Designware IP.
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This controller can work either as EP or RC. In order to enable
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host-specific features PCIE_DW_PLAT_HOST must be selected and in
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order to enable device-specific features PCI_DW_PLAT_EP must be
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selected.
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config PCI_EXYNOS
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bool "Samsung Exynos PCIe controller"
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depends on SOC_EXYNOS5440 || COMPILE_TEST
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depends on PCI_MSI_IRQ_DOMAIN
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select PCIE_DW_HOST
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config PCI_IMX6
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bool "Freescale i.MX6/7/8 PCIe controller"
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depends on ARCH_MXC || COMPILE_TEST
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depends on PCI_MSI_IRQ_DOMAIN
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select PCIE_DW_HOST
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config PCIE_SPEAR13XX
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bool "STMicroelectronics SPEAr PCIe controller"
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depends on ARCH_SPEAR13XX || COMPILE_TEST
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depends on PCI_MSI_IRQ_DOMAIN
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select PCIE_DW_HOST
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help
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Say Y here if you want PCIe support on SPEAr13XX SoCs.
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config PCI_KEYSTONE
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bool
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config PCI_KEYSTONE_HOST
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bool "PCI Keystone Host Mode"
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depends on ARCH_KEYSTONE || ARCH_K3 || ((ARM || ARM64) && COMPILE_TEST)
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depends on PCI_MSI_IRQ_DOMAIN
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select PCIE_DW_HOST
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select PCI_KEYSTONE
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default y
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help
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Enables support for the PCIe controller in the Keystone SoC to
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work in host mode. The PCI controller on Keystone is based on
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DesignWare hardware and therefore the driver re-uses the
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DesignWare core functions to implement the driver.
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config PCI_KEYSTONE_EP
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bool "PCI Keystone Endpoint Mode"
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depends on ARCH_KEYSTONE || ARCH_K3 || ((ARM || ARM64) && COMPILE_TEST)
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depends on PCI_ENDPOINT
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select PCIE_DW_EP
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select PCI_KEYSTONE
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help
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Enables support for the PCIe controller in the Keystone SoC to
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work in endpoint mode. The PCI controller on Keystone is based
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on DesignWare hardware and therefore the driver re-uses the
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DesignWare core functions to implement the driver.
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config PCI_LAYERSCAPE
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bool "Freescale Layerscape PCIe controller - Host mode"
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depends on OF && (ARM || ARCH_LAYERSCAPE || COMPILE_TEST)
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depends on PCI_MSI_IRQ_DOMAIN
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select MFD_SYSCON
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select PCIE_DW_HOST
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help
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Say Y here if you want to enable PCIe controller support on Layerscape
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SoCs to work in Host mode.
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This controller can work either as EP or RC. The RCW[HOST_AGT_PEX]
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determines which PCIe controller works in EP mode and which PCIe
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controller works in RC mode.
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config PCI_LAYERSCAPE_EP
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bool "Freescale Layerscape PCIe controller - Endpoint mode"
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depends on OF && (ARM || ARCH_LAYERSCAPE || COMPILE_TEST)
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depends on PCI_ENDPOINT
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select PCIE_DW_EP
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help
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Say Y here if you want to enable PCIe controller support on Layerscape
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SoCs to work in Endpoint mode.
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This controller can work either as EP or RC. The RCW[HOST_AGT_PEX]
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determines which PCIe controller works in EP mode and which PCIe
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controller works in RC mode.
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config PCI_HISI
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depends on OF && (ARM64 || COMPILE_TEST)
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bool "HiSilicon Hip05 and Hip06 SoCs PCIe controllers"
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depends on PCI_MSI_IRQ_DOMAIN
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select PCIE_DW_HOST
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select PCI_HOST_COMMON
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help
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Say Y here if you want PCIe controller support on HiSilicon
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Hip05 and Hip06 SoCs
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config PCIE_QCOM
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bool "Qualcomm PCIe controller"
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depends on OF && (ARCH_QCOM || COMPILE_TEST)
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depends on PCI_MSI_IRQ_DOMAIN
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select PCIE_DW_HOST
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help
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Say Y here to enable PCIe controller support on Qualcomm SoCs. The
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PCIe controller uses the DesignWare core plus Qualcomm-specific
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hardware wrappers.
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config PCIE_ARMADA_8K
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bool "Marvell Armada-8K PCIe controller"
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depends on ARCH_MVEBU || COMPILE_TEST
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depends on PCI_MSI_IRQ_DOMAIN
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select PCIE_DW_HOST
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help
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Say Y here if you want to enable PCIe controller support on
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Armada-8K SoCs. The PCIe controller on Armada-8K is based on
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DesignWare hardware and therefore the driver re-uses the
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DesignWare core functions to implement the driver.
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config PCIE_ARTPEC6
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bool
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config PCIE_ARTPEC6_HOST
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bool "Axis ARTPEC-6 PCIe controller Host Mode"
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depends on MACH_ARTPEC6 || COMPILE_TEST
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depends on PCI_MSI_IRQ_DOMAIN
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select PCIE_DW_HOST
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select PCIE_ARTPEC6
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help
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Enables support for the PCIe controller in the ARTPEC-6 SoC to work in
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host mode. This uses the DesignWare core.
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config PCIE_ARTPEC6_EP
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bool "Axis ARTPEC-6 PCIe controller Endpoint Mode"
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depends on MACH_ARTPEC6 || COMPILE_TEST
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depends on PCI_ENDPOINT
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select PCIE_DW_EP
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select PCIE_ARTPEC6
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help
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Enables support for the PCIe controller in the ARTPEC-6 SoC to work in
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endpoint mode. This uses the DesignWare core.
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config PCIE_KIRIN
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depends on OF && (ARM64 || COMPILE_TEST)
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bool "HiSilicon Kirin series SoCs PCIe controllers"
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depends on PCI_MSI_IRQ_DOMAIN
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select PCIE_DW_HOST
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help
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Say Y here if you want PCIe controller support
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on HiSilicon Kirin series SoCs.
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config PCIE_HISI_STB
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bool "HiSilicon STB SoCs PCIe controllers"
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depends on ARCH_HISI || COMPILE_TEST
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depends on PCI_MSI_IRQ_DOMAIN
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select PCIE_DW_HOST
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help
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Say Y here if you want PCIe controller support on HiSilicon STB SoCs
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config PCI_MESON
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bool "MESON PCIe controller"
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depends on PCI_MSI_IRQ_DOMAIN
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select PCIE_DW_HOST
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help
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Say Y here if you want to enable PCI controller support on Amlogic
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SoCs. The PCI controller on Amlogic is based on DesignWare hardware
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and therefore the driver re-uses the DesignWare core functions to
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implement the driver.
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config PCIE_TEGRA194
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tristate "NVIDIA Tegra194 (and later) PCIe controller"
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depends on ARCH_TEGRA_194_SOC || COMPILE_TEST
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depends on PCI_MSI_IRQ_DOMAIN
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select PCIE_DW_HOST
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select PHY_TEGRA194_P2U
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help
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Say Y here if you want support for DesignWare core based PCIe host
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controller found in NVIDIA Tegra194 SoC.
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config PCIE_UNIPHIER
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bool "Socionext UniPhier PCIe controllers"
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depends on ARCH_UNIPHIER || COMPILE_TEST
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depends on OF && HAS_IOMEM
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depends on PCI_MSI_IRQ_DOMAIN
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select PCIE_DW_HOST
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help
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Say Y here if you want PCIe controller support on UniPhier SoCs.
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This driver supports LD20 and PXs3 SoCs.
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config PCIE_AL
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bool "Amazon Annapurna Labs PCIe controller"
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depends on OF && (ARM64 || COMPILE_TEST)
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depends on PCI_MSI_IRQ_DOMAIN
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select PCIE_DW_HOST
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help
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Say Y here to enable support of the Amazon's Annapurna Labs PCIe
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controller IP on Amazon SoCs. The PCIe controller uses the DesignWare
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core plus Annapurna Labs proprietary hardware wrappers. This is
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required only for DT-based platforms. ACPI platforms with the
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Annapurna Labs PCIe controller don't need to enable this.
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endmenu
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