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f4c321eb26
Commit 72c5839515 (arm64: gicv3: Allow GICv3 compilation with
older binutils) changed the way we express the GICv3 system registers,
but couldn't change the occurences used by KVM as the code wasn't
merged yet.
Just fix the accessors.
Cc: Will Deacon <will.deacon@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Christoffer Dall <christoffer.dall@linaro.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
268 lines
6.4 KiB
ArmAsm
268 lines
6.4 KiB
ArmAsm
/*
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* Copyright (C) 2012,2013 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/linkage.h>
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#include <linux/irqchip/arm-gic-v3.h>
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#include <asm/assembler.h>
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#include <asm/memory.h>
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#include <asm/asm-offsets.h>
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#include <asm/kvm.h>
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#include <asm/kvm_asm.h>
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#include <asm/kvm_arm.h>
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.text
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.pushsection .hyp.text, "ax"
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/*
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* We store LRs in reverse order to let the CPU deal with streaming
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* access. Use this macro to make it look saner...
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*/
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#define LR_OFFSET(n) (VGIC_V3_CPU_LR + (15 - n) * 8)
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/*
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* Save the VGIC CPU state into memory
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* x0: Register pointing to VCPU struct
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* Do not corrupt x1!!!
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*/
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.macro save_vgic_v3_state
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// Compute the address of struct vgic_cpu
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add x3, x0, #VCPU_VGIC_CPU
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// Make sure stores to the GIC via the memory mapped interface
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// are now visible to the system register interface
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dsb st
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// Save all interesting registers
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mrs_s x4, ICH_HCR_EL2
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mrs_s x5, ICH_VMCR_EL2
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mrs_s x6, ICH_MISR_EL2
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mrs_s x7, ICH_EISR_EL2
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mrs_s x8, ICH_ELSR_EL2
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str w4, [x3, #VGIC_V3_CPU_HCR]
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str w5, [x3, #VGIC_V3_CPU_VMCR]
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str w6, [x3, #VGIC_V3_CPU_MISR]
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str w7, [x3, #VGIC_V3_CPU_EISR]
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str w8, [x3, #VGIC_V3_CPU_ELRSR]
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msr_s ICH_HCR_EL2, xzr
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mrs_s x21, ICH_VTR_EL2
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mvn w22, w21
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ubfiz w23, w22, 2, 4 // w23 = (15 - ListRegs) * 4
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adr x24, 1f
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add x24, x24, x23
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br x24
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1:
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mrs_s x20, ICH_LR15_EL2
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mrs_s x19, ICH_LR14_EL2
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mrs_s x18, ICH_LR13_EL2
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mrs_s x17, ICH_LR12_EL2
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mrs_s x16, ICH_LR11_EL2
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mrs_s x15, ICH_LR10_EL2
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mrs_s x14, ICH_LR9_EL2
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mrs_s x13, ICH_LR8_EL2
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mrs_s x12, ICH_LR7_EL2
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mrs_s x11, ICH_LR6_EL2
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mrs_s x10, ICH_LR5_EL2
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mrs_s x9, ICH_LR4_EL2
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mrs_s x8, ICH_LR3_EL2
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mrs_s x7, ICH_LR2_EL2
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mrs_s x6, ICH_LR1_EL2
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mrs_s x5, ICH_LR0_EL2
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adr x24, 1f
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add x24, x24, x23
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br x24
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1:
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str x20, [x3, #LR_OFFSET(15)]
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str x19, [x3, #LR_OFFSET(14)]
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str x18, [x3, #LR_OFFSET(13)]
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str x17, [x3, #LR_OFFSET(12)]
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str x16, [x3, #LR_OFFSET(11)]
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str x15, [x3, #LR_OFFSET(10)]
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str x14, [x3, #LR_OFFSET(9)]
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str x13, [x3, #LR_OFFSET(8)]
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str x12, [x3, #LR_OFFSET(7)]
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str x11, [x3, #LR_OFFSET(6)]
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str x10, [x3, #LR_OFFSET(5)]
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str x9, [x3, #LR_OFFSET(4)]
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str x8, [x3, #LR_OFFSET(3)]
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str x7, [x3, #LR_OFFSET(2)]
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str x6, [x3, #LR_OFFSET(1)]
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str x5, [x3, #LR_OFFSET(0)]
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tbnz w21, #29, 6f // 6 bits
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tbz w21, #30, 5f // 5 bits
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// 7 bits
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mrs_s x20, ICH_AP0R3_EL2
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str w20, [x3, #(VGIC_V3_CPU_AP0R + 3*4)]
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mrs_s x19, ICH_AP0R2_EL2
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str w19, [x3, #(VGIC_V3_CPU_AP0R + 2*4)]
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6: mrs_s x18, ICH_AP0R1_EL2
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str w18, [x3, #(VGIC_V3_CPU_AP0R + 1*4)]
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5: mrs_s x17, ICH_AP0R0_EL2
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str w17, [x3, #VGIC_V3_CPU_AP0R]
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tbnz w21, #29, 6f // 6 bits
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tbz w21, #30, 5f // 5 bits
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// 7 bits
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mrs_s x20, ICH_AP1R3_EL2
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str w20, [x3, #(VGIC_V3_CPU_AP1R + 3*4)]
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mrs_s x19, ICH_AP1R2_EL2
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str w19, [x3, #(VGIC_V3_CPU_AP1R + 2*4)]
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6: mrs_s x18, ICH_AP1R1_EL2
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str w18, [x3, #(VGIC_V3_CPU_AP1R + 1*4)]
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5: mrs_s x17, ICH_AP1R0_EL2
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str w17, [x3, #VGIC_V3_CPU_AP1R]
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// Restore SRE_EL1 access and re-enable SRE at EL1.
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mrs_s x5, ICC_SRE_EL2
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orr x5, x5, #ICC_SRE_EL2_ENABLE
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msr_s ICC_SRE_EL2, x5
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isb
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mov x5, #1
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msr_s ICC_SRE_EL1, x5
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.endm
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/*
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* Restore the VGIC CPU state from memory
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* x0: Register pointing to VCPU struct
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*/
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.macro restore_vgic_v3_state
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// Disable SRE_EL1 access. Necessary, otherwise
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// ICH_VMCR_EL2.VFIQEn becomes one, and FIQ happens...
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msr_s ICC_SRE_EL1, xzr
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isb
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// Compute the address of struct vgic_cpu
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add x3, x0, #VCPU_VGIC_CPU
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// Restore all interesting registers
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ldr w4, [x3, #VGIC_V3_CPU_HCR]
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ldr w5, [x3, #VGIC_V3_CPU_VMCR]
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msr_s ICH_HCR_EL2, x4
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msr_s ICH_VMCR_EL2, x5
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mrs_s x21, ICH_VTR_EL2
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tbnz w21, #29, 6f // 6 bits
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tbz w21, #30, 5f // 5 bits
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// 7 bits
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ldr w20, [x3, #(VGIC_V3_CPU_AP1R + 3*4)]
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msr_s ICH_AP1R3_EL2, x20
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ldr w19, [x3, #(VGIC_V3_CPU_AP1R + 2*4)]
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msr_s ICH_AP1R2_EL2, x19
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6: ldr w18, [x3, #(VGIC_V3_CPU_AP1R + 1*4)]
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msr_s ICH_AP1R1_EL2, x18
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5: ldr w17, [x3, #VGIC_V3_CPU_AP1R]
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msr_s ICH_AP1R0_EL2, x17
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tbnz w21, #29, 6f // 6 bits
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tbz w21, #30, 5f // 5 bits
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// 7 bits
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ldr w20, [x3, #(VGIC_V3_CPU_AP0R + 3*4)]
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msr_s ICH_AP0R3_EL2, x20
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ldr w19, [x3, #(VGIC_V3_CPU_AP0R + 2*4)]
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msr_s ICH_AP0R2_EL2, x19
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6: ldr w18, [x3, #(VGIC_V3_CPU_AP0R + 1*4)]
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msr_s ICH_AP0R1_EL2, x18
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5: ldr w17, [x3, #VGIC_V3_CPU_AP0R]
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msr_s ICH_AP0R0_EL2, x17
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and w22, w21, #0xf
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mvn w22, w21
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ubfiz w23, w22, 2, 4 // w23 = (15 - ListRegs) * 4
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adr x24, 1f
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add x24, x24, x23
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br x24
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1:
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ldr x20, [x3, #LR_OFFSET(15)]
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ldr x19, [x3, #LR_OFFSET(14)]
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ldr x18, [x3, #LR_OFFSET(13)]
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ldr x17, [x3, #LR_OFFSET(12)]
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ldr x16, [x3, #LR_OFFSET(11)]
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ldr x15, [x3, #LR_OFFSET(10)]
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ldr x14, [x3, #LR_OFFSET(9)]
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ldr x13, [x3, #LR_OFFSET(8)]
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ldr x12, [x3, #LR_OFFSET(7)]
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ldr x11, [x3, #LR_OFFSET(6)]
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ldr x10, [x3, #LR_OFFSET(5)]
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ldr x9, [x3, #LR_OFFSET(4)]
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ldr x8, [x3, #LR_OFFSET(3)]
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ldr x7, [x3, #LR_OFFSET(2)]
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ldr x6, [x3, #LR_OFFSET(1)]
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ldr x5, [x3, #LR_OFFSET(0)]
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adr x24, 1f
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add x24, x24, x23
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br x24
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1:
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msr_s ICH_LR15_EL2, x20
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msr_s ICH_LR14_EL2, x19
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msr_s ICH_LR13_EL2, x18
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msr_s ICH_LR12_EL2, x17
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msr_s ICH_LR11_EL2, x16
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msr_s ICH_LR10_EL2, x15
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msr_s ICH_LR9_EL2, x14
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msr_s ICH_LR8_EL2, x13
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msr_s ICH_LR7_EL2, x12
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msr_s ICH_LR6_EL2, x11
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msr_s ICH_LR5_EL2, x10
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msr_s ICH_LR4_EL2, x9
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msr_s ICH_LR3_EL2, x8
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msr_s ICH_LR2_EL2, x7
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msr_s ICH_LR1_EL2, x6
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msr_s ICH_LR0_EL2, x5
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// Ensure that the above will have reached the
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// (re)distributors. This ensure the guest will read
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// the correct values from the memory-mapped interface.
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isb
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dsb sy
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// Prevent the guest from touching the GIC system registers
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mrs_s x5, ICC_SRE_EL2
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and x5, x5, #~ICC_SRE_EL2_ENABLE
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msr_s ICC_SRE_EL2, x5
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.endm
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ENTRY(__save_vgic_v3_state)
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save_vgic_v3_state
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ret
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ENDPROC(__save_vgic_v3_state)
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ENTRY(__restore_vgic_v3_state)
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restore_vgic_v3_state
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ret
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ENDPROC(__restore_vgic_v3_state)
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ENTRY(__vgic_v3_get_ich_vtr_el2)
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mrs_s x0, ICH_VTR_EL2
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ret
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ENDPROC(__vgic_v3_get_ich_vtr_el2)
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.popsection
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