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e7b37a522a
Allow mux_reg offset zero to be a valid pin_id, on imx7d mux_conf reg offset is zero for iomuxc-lspr controller Signed-off-by: Adrian Alonso <aalonso@freescale.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
103 lines
2.6 KiB
C
103 lines
2.6 KiB
C
/*
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* IMX pinmux core definitions
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*
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* Copyright (C) 2012 Freescale Semiconductor, Inc.
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* Copyright (C) 2012 Linaro Ltd.
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*
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* Author: Dong Aisheng <dong.aisheng@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef __DRIVERS_PINCTRL_IMX_H
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#define __DRIVERS_PINCTRL_IMX_H
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struct platform_device;
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/**
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* struct imx_pin_group - describes a single i.MX pin
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* @pin: the pin_id of this pin
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* @mux_mode: the mux mode for this pin.
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* @input_reg: the select input register offset for this pin if any
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* 0 if no select input setting needed.
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* @input_val: the select input value for this pin.
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* @configs: the config for this pin.
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*/
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struct imx_pin {
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unsigned int pin;
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unsigned int mux_mode;
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u16 input_reg;
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unsigned int input_val;
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unsigned long config;
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};
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/**
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* struct imx_pin_group - describes an IMX pin group
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* @name: the name of this specific pin group
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* @npins: the number of pins in this group array, i.e. the number of
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* elements in .pins so we can iterate over that array
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* @pin_ids: array of pin_ids. pinctrl forces us to maintain such an array
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* @pins: array of pins
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*/
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struct imx_pin_group {
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const char *name;
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unsigned npins;
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unsigned int *pin_ids;
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struct imx_pin *pins;
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};
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/**
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* struct imx_pmx_func - describes IMX pinmux functions
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* @name: the name of this specific function
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* @groups: corresponding pin groups
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* @num_groups: the number of groups
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*/
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struct imx_pmx_func {
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const char *name;
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const char **groups;
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unsigned num_groups;
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};
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/**
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* struct imx_pin_reg - describe a pin reg map
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* @mux_reg: mux register offset
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* @conf_reg: config register offset
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*/
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struct imx_pin_reg {
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s16 mux_reg;
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s16 conf_reg;
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};
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struct imx_pinctrl_soc_info {
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struct device *dev;
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const struct pinctrl_pin_desc *pins;
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unsigned int npins;
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struct imx_pin_reg *pin_regs;
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struct imx_pin_group *groups;
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unsigned int ngroups;
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unsigned int group_index;
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struct imx_pmx_func *functions;
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unsigned int nfunctions;
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unsigned int flags;
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};
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#define SHARE_MUX_CONF_REG 0x1
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#define ZERO_OFFSET_VALID 0x2
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#define NO_MUX 0x0
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#define NO_PAD 0x0
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#define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
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#define PAD_CTL_MASK(len) ((1 << len) - 1)
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#define IMX_MUX_MASK 0x7
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#define IOMUXC_CONFIG_SION (0x1 << 4)
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int imx_pinctrl_probe(struct platform_device *pdev,
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struct imx_pinctrl_soc_info *info);
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int imx_pinctrl_remove(struct platform_device *pdev);
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#endif /* __DRIVERS_PINCTRL_IMX_H */
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