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This adds a new DRM driver for the Faraday Technology TVE200 block. This "TV Encoder" encodes a ITU-T BT.656 stream and can be found in the StorLink SL3516 (later Cortina Systems CS3516) as well as the Grain Media GM8180. I do not have definitive word from anyone at Faraday that this IP block is theirs, but it bears the hallmark of their 3-digit version code (200) and is used in two SoCs from completely different companies. (Grain Media was fully owned by Faraday until it was transferred to NovoTek this january, and Faraday did lots of work on the StorLink SoCs.) The D-Link DIR-685 uses this in connection with the Ilitek ILI9322 panel driver that supports BT.656 input, while the GM8180 apparently has been used with the Cirrus Logic CS4954 digital video encoder. The oldest user seems to be something called Techwall 2835. This driver is heavily inspired by Eric Anholt's PL111 driver and therefore I have mentioned all the ancestor authors in the header file. Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20170820100557.24991-2-linus.walleij@linaro.org
130 lines
4.8 KiB
C
130 lines
4.8 KiB
C
/*
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* Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
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* Parts of this file were based on sources as follows:
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*
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* Copyright (C) 2006-2008 Intel Corporation
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* Copyright (C) 2007 Amos Lee <amos_lee@storlinksemi.com>
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* Copyright (C) 2007 Dave Airlie <airlied@linux.ie>
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* Copyright (C) 2011 Texas Instruments
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* Copyright (C) 2017 Eric Anholt
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*
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* This program is free software and is provided to you under the terms of the
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* GNU General Public License version 2 as published by the Free Software
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* Foundation, and any use by you of this program is subject to the terms of
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* such GNU licence.
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*/
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#ifndef _TVE200_DRM_H_
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#define _TVE200_DRM_H_
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/* Bits 2-31 are valid physical base addresses */
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#define TVE200_Y_FRAME_BASE_ADDR 0x00
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#define TVE200_U_FRAME_BASE_ADDR 0x04
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#define TVE200_V_FRAME_BASE_ADDR 0x08
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#define TVE200_INT_EN 0x0C
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#define TVE200_INT_CLR 0x10
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#define TVE200_INT_STAT 0x14
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#define TVE200_INT_BUS_ERR BIT(7)
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#define TVE200_INT_V_STATUS BIT(6) /* vertical blank */
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#define TVE200_INT_V_NEXT_FRAME BIT(5)
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#define TVE200_INT_U_NEXT_FRAME BIT(4)
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#define TVE200_INT_Y_NEXT_FRAME BIT(3)
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#define TVE200_INT_V_FIFO_UNDERRUN BIT(2)
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#define TVE200_INT_U_FIFO_UNDERRUN BIT(1)
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#define TVE200_INT_Y_FIFO_UNDERRUN BIT(0)
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#define TVE200_FIFO_UNDERRUNS (TVE200_INT_V_FIFO_UNDERRUN | \
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TVE200_INT_U_FIFO_UNDERRUN | \
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TVE200_INT_Y_FIFO_UNDERRUN)
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#define TVE200_CTRL 0x18
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#define TVE200_CTRL_YUV420 BIT(31)
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#define TVE200_CTRL_CSMODE BIT(30)
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#define TVE200_CTRL_NONINTERLACE BIT(28) /* 0 = non-interlace CCIR656 */
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#define TVE200_CTRL_TVCLKP BIT(27) /* Inverted clock phase */
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/* Bits 24..26 define the burst size after arbitration on the bus */
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#define TVE200_CTRL_BURST_4_WORDS (0 << 24)
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#define TVE200_CTRL_BURST_8_WORDS (1 << 24)
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#define TVE200_CTRL_BURST_16_WORDS (2 << 24)
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#define TVE200_CTRL_BURST_32_WORDS (3 << 24)
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#define TVE200_CTRL_BURST_64_WORDS (4 << 24)
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#define TVE200_CTRL_BURST_128_WORDS (5 << 24)
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#define TVE200_CTRL_BURST_256_WORDS (6 << 24)
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#define TVE200_CTRL_BURST_0_WORDS (7 << 24) /* ? */
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/*
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* Bits 16..23 is the retry count*16 before issueing a new AHB transfer
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* on the AHB bus.
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*/
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#define TVE200_CTRL_RETRYCNT_MASK GENMASK(23, 16)
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#define TVE200_CTRL_RETRYCNT_16 (1 << 16)
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#define TVE200_CTRL_BBBP BIT(15) /* 0 = little-endian */
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/* Bits 12..14 define the YCbCr ordering */
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#define TVE200_CTRL_YCBCRODR_CB0Y0CR0Y1 (0 << 12)
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#define TVE200_CTRL_YCBCRODR_Y0CB0Y1CR0 (1 << 12)
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#define TVE200_CTRL_YCBCRODR_CR0Y0CB0Y1 (2 << 12)
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#define TVE200_CTRL_YCBCRODR_Y1CB0Y0CR0 (3 << 12)
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#define TVE200_CTRL_YCBCRODR_CR0Y1CB0Y0 (4 << 12)
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#define TVE200_CTRL_YCBCRODR_Y1CR0Y0CB0 (5 << 12)
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#define TVE200_CTRL_YCBCRODR_CB0Y1CR0Y0 (6 << 12)
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#define TVE200_CTRL_YCBCRODR_Y0CR0Y1CB0 (7 << 12)
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/* Bits 10..11 define the input resolution (framebuffer size) */
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#define TVE200_CTRL_IPRESOL_CIF (0 << 10)
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#define TVE200_CTRL_IPRESOL_VGA (1 << 10)
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#define TVE200_CTRL_IPRESOL_D1 (2 << 10)
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#define TVE200_CTRL_NTSC BIT(9) /* 0 = PAL, 1 = NTSC */
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#define TVE200_CTRL_INTERLACE BIT(8) /* 1 = interlace, only for D1 */
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#define TVE200_IPDMOD_RGB555 (0 << 6) /* TVE200_CTRL_YUV420 = 0 */
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#define TVE200_IPDMOD_RGB565 (1 << 6)
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#define TVE200_IPDMOD_RGB888 (2 << 6)
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#define TVE200_IPDMOD_YUV420 (2 << 6) /* TVE200_CTRL_YUV420 = 1 */
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#define TVE200_IPDMOD_YUV422 (3 << 6)
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/* Bits 4 & 5 define when to fire the vblank IRQ */
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#define TVE200_VSTSTYPE_VSYNC (0 << 4) /* start of vsync */
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#define TVE200_VSTSTYPE_VBP (1 << 4) /* start of v back porch */
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#define TVE200_VSTSTYPE_VAI (2 << 4) /* start of v active image */
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#define TVE200_VSTSTYPE_VFP (3 << 4) /* start of v front porch */
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#define TVE200_VSTSTYPE_BITS (BIT(4) | BIT(5))
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#define TVE200_BGR BIT(1) /* 0 = RGB, 1 = BGR */
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#define TVE200_TVEEN BIT(0) /* Enable TVE block */
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#define TVE200_CTRL_2 0x1c
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#define TVE200_CTRL_3 0x20
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#define TVE200_CTRL_4 0x24
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#define TVE200_CTRL_4_RESET BIT(0) /* triggers reset of TVE200 */
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#include <drm/drm_gem.h>
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#include <drm/drm_simple_kms_helper.h>
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struct tve200_drm_connector {
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struct drm_connector connector;
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struct drm_panel *panel;
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};
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struct tve200_drm_dev_private {
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struct drm_device *drm;
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struct tve200_drm_connector connector;
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struct drm_simple_display_pipe pipe;
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struct drm_fbdev_cma *fbdev;
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void *regs;
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struct clk *pclk;
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struct clk *clk;
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};
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#define to_tve200_connector(x) \
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container_of(x, struct tve200_drm_connector, connector)
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int tve200_display_init(struct drm_device *dev);
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int tve200_enable_vblank(struct drm_device *drm, unsigned int crtc);
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void tve200_disable_vblank(struct drm_device *drm, unsigned int crtc);
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irqreturn_t tve200_irq(int irq, void *data);
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int tve200_connector_init(struct drm_device *dev);
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int tve200_encoder_init(struct drm_device *dev);
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int tve200_dumb_create(struct drm_file *file_priv,
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struct drm_device *dev,
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struct drm_mode_create_dumb *args);
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#endif /* _TVE200_DRM_H_ */
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