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Tegra SPI controller has TX and RX trimmers to tuning the delay of SPI master clock with respect to the data. TX and RX tap values are based on the platform validation across the PVT and the trimmer values vary based on the trace lengths to the corresponding SPI devices. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
62 lines
2.1 KiB
Plaintext
62 lines
2.1 KiB
Plaintext
NVIDIA Tegra114 SPI controller.
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Required properties:
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- compatible : For Tegra114, must contain "nvidia,tegra114-spi".
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Otherwise, must contain '"nvidia,<chip>-spi", "nvidia,tegra114-spi"' where
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<chip> is tegra124, tegra132, or tegra210.
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- reg: Should contain SPI registers location and length.
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- interrupts: Should contain SPI interrupts.
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- clock-names : Must include the following entries:
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- spi
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- resets : Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names : Must include the following entries:
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- spi
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- dmas : Must contain an entry for each entry in clock-names.
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See ../dma/dma.txt for details.
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- dma-names : Must include the following entries:
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- rx
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- tx
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- clocks : Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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Recommended properties:
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- spi-max-frequency: Definition as per
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Documentation/devicetree/bindings/spi/spi-bus.txt
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Optional properties:
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- nvidia,tx-clk-tap-delay: Delays the clock going out to the external device
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with this tap value. This property is used to tune the outgoing data from
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Tegra SPI master with respect to outgoing Tegra SPI master clock.
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Tap values vary based on the platform design trace lengths from Tegra SPI
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to corresponding slave devices. Valid tap values are from 0 thru 63.
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- nvidia,rx-clk-tap-delay: Delays the clock coming in from the external device
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with this tap value. This property is used to adjust the Tegra SPI master
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clock with respect to the data from the SPI slave device.
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Tap values vary based on the platform design trace lengths from Tegra SPI
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to corresponding slave devices. Valid tap values are from 0 thru 63.
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Example:
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spi@7000d600 {
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compatible = "nvidia,tegra114-spi";
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reg = <0x7000d600 0x200>;
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interrupts = <0 82 0x04>;
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spi-max-frequency = <25000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car 44>;
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clock-names = "spi";
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resets = <&tegra_car 44>;
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reset-names = "spi";
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dmas = <&apbdma 16>, <&apbdma 16>;
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dma-names = "rx", "tx";
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<spi-client>@<bus_num> {
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...
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...
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nvidia,rx-clk-tap-delay = <0>;
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nvidia,tx-clk-tap-delay = <16>;
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...
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};
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};
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