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280510f106
The PCI/MSI irq chip callbacks mask/unmask_msi_irq have been renamed to pci_msi_mask/unmask_irq to mark them PCI specific. Rename all usage sites. The conversion helper functions are kept around to avoid conflicts in next and will be removed after merging into mainline. Coccinelle assisted conversion. No functional change. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Chris Metcalf <cmetcalf@tilera.com> Cc: x86@kernel.org Cc: Jiang Liu <jiang.liu@linux.intel.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Mohit Kumar <mohit.kumar@st.com> Cc: Simon Horman <horms@verge.net.au> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Yijing Wang <wangyijing@huawei.com>
447 lines
9.7 KiB
C
447 lines
9.7 KiB
C
/* pci_msi.c: Sparc64 MSI support common layer.
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*
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* Copyright (C) 2007 David S. Miller (davem@davemloft.net)
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*/
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/slab.h>
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#include <linux/irq.h>
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#include "pci_impl.h"
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static irqreturn_t sparc64_msiq_interrupt(int irq, void *cookie)
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{
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struct sparc64_msiq_cookie *msiq_cookie = cookie;
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struct pci_pbm_info *pbm = msiq_cookie->pbm;
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unsigned long msiqid = msiq_cookie->msiqid;
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const struct sparc64_msiq_ops *ops;
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unsigned long orig_head, head;
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int err;
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ops = pbm->msi_ops;
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err = ops->get_head(pbm, msiqid, &head);
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if (unlikely(err < 0))
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goto err_get_head;
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orig_head = head;
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for (;;) {
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unsigned long msi;
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err = ops->dequeue_msi(pbm, msiqid, &head, &msi);
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if (likely(err > 0)) {
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unsigned int irq;
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irq = pbm->msi_irq_table[msi - pbm->msi_first];
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generic_handle_irq(irq);
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}
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if (unlikely(err < 0))
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goto err_dequeue;
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if (err == 0)
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break;
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}
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if (likely(head != orig_head)) {
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err = ops->set_head(pbm, msiqid, head);
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if (unlikely(err < 0))
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goto err_set_head;
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}
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return IRQ_HANDLED;
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err_get_head:
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printk(KERN_EMERG "MSI: Get head on msiqid[%lu] gives error %d\n",
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msiqid, err);
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goto err_out;
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err_dequeue:
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printk(KERN_EMERG "MSI: Dequeue head[%lu] from msiqid[%lu] "
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"gives error %d\n",
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head, msiqid, err);
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goto err_out;
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err_set_head:
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printk(KERN_EMERG "MSI: Set head[%lu] on msiqid[%lu] "
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"gives error %d\n",
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head, msiqid, err);
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goto err_out;
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err_out:
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return IRQ_NONE;
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}
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static u32 pick_msiq(struct pci_pbm_info *pbm)
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{
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static DEFINE_SPINLOCK(rotor_lock);
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unsigned long flags;
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u32 ret, rotor;
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spin_lock_irqsave(&rotor_lock, flags);
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rotor = pbm->msiq_rotor;
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ret = pbm->msiq_first + rotor;
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if (++rotor >= pbm->msiq_num)
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rotor = 0;
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pbm->msiq_rotor = rotor;
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spin_unlock_irqrestore(&rotor_lock, flags);
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return ret;
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}
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static int alloc_msi(struct pci_pbm_info *pbm)
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{
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int i;
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for (i = 0; i < pbm->msi_num; i++) {
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if (!test_and_set_bit(i, pbm->msi_bitmap))
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return i + pbm->msi_first;
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}
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return -ENOENT;
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}
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static void free_msi(struct pci_pbm_info *pbm, int msi_num)
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{
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msi_num -= pbm->msi_first;
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clear_bit(msi_num, pbm->msi_bitmap);
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}
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static struct irq_chip msi_irq = {
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.name = "PCI-MSI",
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.irq_mask = pci_msi_mask_irq,
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.irq_unmask = pci_msi_unmask_irq,
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.irq_enable = pci_msi_unmask_irq,
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.irq_disable = pci_msi_mask_irq,
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/* XXX affinity XXX */
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};
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static int sparc64_setup_msi_irq(unsigned int *irq_p,
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struct pci_dev *pdev,
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struct msi_desc *entry)
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{
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struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
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const struct sparc64_msiq_ops *ops = pbm->msi_ops;
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struct msi_msg msg;
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int msi, err;
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u32 msiqid;
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*irq_p = irq_alloc(0, 0);
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err = -ENOMEM;
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if (!*irq_p)
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goto out_err;
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irq_set_chip_and_handler_name(*irq_p, &msi_irq, handle_simple_irq,
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"MSI");
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err = alloc_msi(pbm);
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if (unlikely(err < 0))
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goto out_irq_free;
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msi = err;
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msiqid = pick_msiq(pbm);
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err = ops->msi_setup(pbm, msiqid, msi,
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(entry->msi_attrib.is_64 ? 1 : 0));
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if (err)
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goto out_msi_free;
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pbm->msi_irq_table[msi - pbm->msi_first] = *irq_p;
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if (entry->msi_attrib.is_64) {
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msg.address_hi = pbm->msi64_start >> 32;
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msg.address_lo = pbm->msi64_start & 0xffffffff;
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} else {
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msg.address_hi = 0;
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msg.address_lo = pbm->msi32_start;
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}
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msg.data = msi;
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irq_set_msi_desc(*irq_p, entry);
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pci_write_msi_msg(*irq_p, &msg);
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return 0;
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out_msi_free:
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free_msi(pbm, msi);
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out_irq_free:
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irq_set_chip(*irq_p, NULL);
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irq_free(*irq_p);
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*irq_p = 0;
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out_err:
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return err;
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}
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static void sparc64_teardown_msi_irq(unsigned int irq,
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struct pci_dev *pdev)
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{
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struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
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const struct sparc64_msiq_ops *ops = pbm->msi_ops;
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unsigned int msi_num;
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int i, err;
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for (i = 0; i < pbm->msi_num; i++) {
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if (pbm->msi_irq_table[i] == irq)
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break;
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}
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if (i >= pbm->msi_num) {
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printk(KERN_ERR "%s: teardown: No MSI for irq %u\n",
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pbm->name, irq);
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return;
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}
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msi_num = pbm->msi_first + i;
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pbm->msi_irq_table[i] = ~0U;
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err = ops->msi_teardown(pbm, msi_num);
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if (err) {
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printk(KERN_ERR "%s: teardown: ops->teardown() on MSI %u, "
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"irq %u, gives error %d\n",
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pbm->name, msi_num, irq, err);
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return;
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}
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free_msi(pbm, msi_num);
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irq_set_chip(irq, NULL);
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irq_free(irq);
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}
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static int msi_bitmap_alloc(struct pci_pbm_info *pbm)
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{
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unsigned long size, bits_per_ulong;
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bits_per_ulong = sizeof(unsigned long) * 8;
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size = (pbm->msi_num + (bits_per_ulong - 1)) & ~(bits_per_ulong - 1);
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size /= 8;
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BUG_ON(size % sizeof(unsigned long));
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pbm->msi_bitmap = kzalloc(size, GFP_KERNEL);
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if (!pbm->msi_bitmap)
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return -ENOMEM;
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return 0;
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}
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static void msi_bitmap_free(struct pci_pbm_info *pbm)
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{
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kfree(pbm->msi_bitmap);
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pbm->msi_bitmap = NULL;
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}
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static int msi_table_alloc(struct pci_pbm_info *pbm)
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{
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int size, i;
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size = pbm->msiq_num * sizeof(struct sparc64_msiq_cookie);
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pbm->msiq_irq_cookies = kzalloc(size, GFP_KERNEL);
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if (!pbm->msiq_irq_cookies)
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return -ENOMEM;
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for (i = 0; i < pbm->msiq_num; i++) {
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struct sparc64_msiq_cookie *p;
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p = &pbm->msiq_irq_cookies[i];
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p->pbm = pbm;
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p->msiqid = pbm->msiq_first + i;
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}
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size = pbm->msi_num * sizeof(unsigned int);
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pbm->msi_irq_table = kzalloc(size, GFP_KERNEL);
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if (!pbm->msi_irq_table) {
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kfree(pbm->msiq_irq_cookies);
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pbm->msiq_irq_cookies = NULL;
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return -ENOMEM;
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}
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return 0;
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}
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static void msi_table_free(struct pci_pbm_info *pbm)
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{
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kfree(pbm->msiq_irq_cookies);
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pbm->msiq_irq_cookies = NULL;
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kfree(pbm->msi_irq_table);
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pbm->msi_irq_table = NULL;
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}
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static int bringup_one_msi_queue(struct pci_pbm_info *pbm,
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const struct sparc64_msiq_ops *ops,
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unsigned long msiqid,
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unsigned long devino)
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{
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int irq = ops->msiq_build_irq(pbm, msiqid, devino);
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int err, nid;
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if (irq < 0)
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return irq;
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nid = pbm->numa_node;
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if (nid != -1) {
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cpumask_t numa_mask;
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cpumask_copy(&numa_mask, cpumask_of_node(nid));
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irq_set_affinity(irq, &numa_mask);
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}
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err = request_irq(irq, sparc64_msiq_interrupt, 0,
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"MSIQ",
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&pbm->msiq_irq_cookies[msiqid - pbm->msiq_first]);
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if (err)
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return err;
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return 0;
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}
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static int sparc64_bringup_msi_queues(struct pci_pbm_info *pbm,
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const struct sparc64_msiq_ops *ops)
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{
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int i;
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for (i = 0; i < pbm->msiq_num; i++) {
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unsigned long msiqid = i + pbm->msiq_first;
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unsigned long devino = i + pbm->msiq_first_devino;
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int err;
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err = bringup_one_msi_queue(pbm, ops, msiqid, devino);
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if (err)
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return err;
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}
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return 0;
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}
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void sparc64_pbm_msi_init(struct pci_pbm_info *pbm,
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const struct sparc64_msiq_ops *ops)
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{
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const u32 *val;
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int len;
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val = of_get_property(pbm->op->dev.of_node, "#msi-eqs", &len);
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if (!val || len != 4)
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goto no_msi;
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pbm->msiq_num = *val;
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if (pbm->msiq_num) {
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const struct msiq_prop {
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u32 first_msiq;
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u32 num_msiq;
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u32 first_devino;
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} *mqp;
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const struct msi_range_prop {
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u32 first_msi;
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u32 num_msi;
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} *mrng;
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const struct addr_range_prop {
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u32 msi32_high;
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u32 msi32_low;
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u32 msi32_len;
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u32 msi64_high;
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u32 msi64_low;
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u32 msi64_len;
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} *arng;
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val = of_get_property(pbm->op->dev.of_node, "msi-eq-size", &len);
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if (!val || len != 4)
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goto no_msi;
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pbm->msiq_ent_count = *val;
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mqp = of_get_property(pbm->op->dev.of_node,
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"msi-eq-to-devino", &len);
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if (!mqp)
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mqp = of_get_property(pbm->op->dev.of_node,
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"msi-eq-devino", &len);
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if (!mqp || len != sizeof(struct msiq_prop))
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goto no_msi;
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pbm->msiq_first = mqp->first_msiq;
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pbm->msiq_first_devino = mqp->first_devino;
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val = of_get_property(pbm->op->dev.of_node, "#msi", &len);
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if (!val || len != 4)
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goto no_msi;
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pbm->msi_num = *val;
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mrng = of_get_property(pbm->op->dev.of_node, "msi-ranges", &len);
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if (!mrng || len != sizeof(struct msi_range_prop))
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goto no_msi;
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pbm->msi_first = mrng->first_msi;
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val = of_get_property(pbm->op->dev.of_node, "msi-data-mask", &len);
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if (!val || len != 4)
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goto no_msi;
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pbm->msi_data_mask = *val;
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val = of_get_property(pbm->op->dev.of_node, "msix-data-width", &len);
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if (!val || len != 4)
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goto no_msi;
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pbm->msix_data_width = *val;
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arng = of_get_property(pbm->op->dev.of_node, "msi-address-ranges",
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&len);
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if (!arng || len != sizeof(struct addr_range_prop))
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goto no_msi;
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pbm->msi32_start = ((u64)arng->msi32_high << 32) |
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(u64) arng->msi32_low;
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pbm->msi64_start = ((u64)arng->msi64_high << 32) |
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(u64) arng->msi64_low;
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pbm->msi32_len = arng->msi32_len;
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pbm->msi64_len = arng->msi64_len;
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if (msi_bitmap_alloc(pbm))
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goto no_msi;
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if (msi_table_alloc(pbm)) {
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msi_bitmap_free(pbm);
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goto no_msi;
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}
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if (ops->msiq_alloc(pbm)) {
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msi_table_free(pbm);
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msi_bitmap_free(pbm);
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goto no_msi;
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}
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if (sparc64_bringup_msi_queues(pbm, ops)) {
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ops->msiq_free(pbm);
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msi_table_free(pbm);
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msi_bitmap_free(pbm);
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goto no_msi;
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}
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printk(KERN_INFO "%s: MSI Queue first[%u] num[%u] count[%u] "
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"devino[0x%x]\n",
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pbm->name,
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pbm->msiq_first, pbm->msiq_num,
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pbm->msiq_ent_count,
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pbm->msiq_first_devino);
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printk(KERN_INFO "%s: MSI first[%u] num[%u] mask[0x%x] "
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"width[%u]\n",
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pbm->name,
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pbm->msi_first, pbm->msi_num, pbm->msi_data_mask,
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pbm->msix_data_width);
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printk(KERN_INFO "%s: MSI addr32[0x%llx:0x%x] "
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"addr64[0x%llx:0x%x]\n",
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pbm->name,
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pbm->msi32_start, pbm->msi32_len,
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pbm->msi64_start, pbm->msi64_len);
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printk(KERN_INFO "%s: MSI queues at RA [%016lx]\n",
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pbm->name,
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__pa(pbm->msi_queues));
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pbm->msi_ops = ops;
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pbm->setup_msi_irq = sparc64_setup_msi_irq;
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pbm->teardown_msi_irq = sparc64_teardown_msi_irq;
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}
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return;
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no_msi:
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pbm->msiq_num = 0;
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printk(KERN_INFO "%s: No MSI support.\n", pbm->name);
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}
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