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1009aa1205
This tag contains some major improvements to the RISC-V port, including the necessary interrupt controller and timer support to actually make it to userspace. Support for three devices has been added: * Support for the ISA-mandated timers on RISC-V systems. * Support for the ISA-mandated first-level interrupt controller on RISC-V systems, which is handled as part of our core arch code because it's very small and tightly tied to the ISA. * Support for SiFive's platform-level interrupt controller, which talks to the actual devices. In addition to these new devices, there are a handful of cleanups all over the RISC-V tree: * Build fixes for various configurations * A fix to the vDSO build's makefile so it respects CFLAGS. * The addition of __lshrti3, a libgcc derived function necessary for some 32-bit configurations. * !SMP && PERF_EVENTS * Cleanups to the arch code to remove the remnants of old versions of the drivers that were just properly submitted. * Some dead code from the timer driver, most of which wasn't ever even compiled. * Cleanups of some interrupt #defines, which are now local to the interrupt handling code. * Fixes to ptrace(), which while not being sufficient to fully make GDB work are at least sufficient to get simple GDB tasks to work. * Early printk support via RISC-V's architecturally mandated SBI console device. * A fix to our early debug trap handler to ensure it's always aligned. These patches have all been through a fairly extensive review process, but as this enables a whole pile of functionality (ie, userspace) I'm confident we'll need to submit a few more patches. The only concrete issues I know about are the sys_riscv_flush_icache patches, but as I managed to screw those up on Friday I figured it'd be best to let them bake another week. This tag boots a Fedora root filesystem on QEMU's master branch for me, and before this morning's rebase (from 4.18-rc8 to 4.18) it booted on the HiFive Unleashed. Thanks to Christoph Hellwig and the other guys at WD for getting the new drivers in shape! -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEAM520YNJYN/OiG3470yhUCzLq0EFAltx3HcTHHBhbG1lckBk YWJiZWx0LmNvbQAKCRDvTKFQLMurQc7nEACh8NCRLyXHOAQefomb+BUx+DJXweau lhTiPexB7+3ZAT6FvL8BgHFu3qMsgZ8iI5pxIz7tap2WRTlakRABLes7c3xQPI4a 3rDbZFE78lQDNY0Kj8iUpvYr0aOfMcC8aoD30qQHaWZVgYZvaZGD3Sar6VbTyaNe 5F5lRaiAtrMmHNio/fXQvnMP83nc1Nxzc4q8VeRjmufc0CvGZUs3L2ZRVx1phwav VedQFsrNHlcyulBv9rQXzaeyvVn+FNKlu4c/9sI6xsGZofGZjOqub1vjURuEfTc5 4AtdFMN0Xb2TYCK277Fr/FY/VEHGXCV+3hGc2U62hnpBtRgGERn7gQUimCJD5b+V gpXZGjtLvTXp9a4N6+ThC/oqvr72aLzInNap95MFK5xSMx/4AdCG7u63sd2qLtkL tlYho+Hd50ImIlUCTs6pfjzmgTMLW2huVJhDNx2lt9OUvNNYjTc4mjEK2WK8DUC7 aUMcHYZMn3hJFNwvd5xTxLPua4ahhhYTyfzHwnMiND4ZjdUnxtrKNj46HjSPqMp9 mgKOkv3G0a021gYODI/dweYI1SV2my814fQHZW4rcFYM2lLwrn2cPMMGezAJF9sR mbLHW6ZxJrtd9m+RZsJB9Z3QnBs68yIqTOBPRRFM5egwt9s9y+19HnBDVe1hj8/j OpmZ/qXCqQt+jA== =PfnC -----END PGP SIGNATURE----- Merge tag 'riscv-for-linus-4.19-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux Pull RISC-V updates from Palmer Dabbelt: "This contains some major improvements to the RISC-V port, including the necessary interrupt controller and timer support to actually make it to userspace. Support for three devices has been added: - the ISA-mandated timers on RISC-V systems. - the ISA-mandated first-level interrupt controller on RISC-V systems, which is handled as part of our core arch code because it's very small and tightly tied to the ISA. - SiFive's platform-level interrupt controller, which talks to the actual devices. In addition to these new devices, there are a handful of cleanups all over the RISC-V tree: - build fixes for various configurations: * A fix to the vDSO build's makefile so it respects CFLAGS. * The addition of __lshrti3, a libgcc derived function necessary for some 32-bit configurations. * !SMP && PERF_EVENTS - Cleanups to the arch code to remove the remnants of old versions of the drivers that were just properly submitted. * Some dead code from the timer driver, most of which wasn't ever even compiled. * Cleanups of some interrupt #defines, which are now local to the interrupt handling code. - Fixes to ptrace(), which while not being sufficient to fully make GDB work are at least sufficient to get simple GDB tasks to work. - Early printk support via RISC-V's architecturally mandated SBI console device. - A fix to our early debug trap handler to ensure it's always aligned. These patches have all been through a fairly extensive review process, but as this enables a whole pile of functionality (ie, userspace) I'm confident we'll need to submit a few more patches. The only concrete issues I know about are the sys_riscv_flush_icache patches, but as I managed to screw those up on Friday I figured it'd be best to let them bake another week. This tag boots a Fedora root filesystem on QEMU's master branch for me, and before this morning's rebase (from 4.18-rc8 to 4.18) it booted on the HiFive Unleashed. Thanks to Christoph Hellwig and the other guys at WD for getting the new drivers in shape!" * tag 'riscv-for-linus-4.19-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux: dt-bindings: interrupt-controller: SiFive Plaform Level Interrupt Controller dt-bindings: interrupt-controller: RISC-V local interrupt controller RISC-V: Fix !CONFIG_SMP compilation error irqchip: add a SiFive PLIC driver RISC-V: Add the directive for alignment of stvec's value clocksource: new RISC-V SBI timer driver RISC-V: implement low-level interrupt handling RISC-V: add a definition for the SIE SEIE bit RISC-V: remove INTERRUPT_CAUSE_* defines from asm/irq.h RISC-V: simplify software interrupt / IPI code RISC-V: remove timer leftovers RISC-V: Add early printk support via the SBI console RISC-V: Don't increment sepc after breakpoint. RISC-V: implement __lshrti3. RISC-V: Use KBUILD_CFLAGS instead of KCFLAGS when building the vDSO |
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.. | ||
alphascale_asm9260-icoll.h | ||
exynos-combiner.c | ||
irq-alpine-msi.c | ||
irq-armada-370-xp.c | ||
irq-aspeed-i2c-ic.c | ||
irq-aspeed-vic.c | ||
irq-ath79-cpu.c | ||
irq-ath79-misc.c | ||
irq-ativic32.c | ||
irq-atmel-aic5.c | ||
irq-atmel-aic-common.c | ||
irq-atmel-aic-common.h | ||
irq-atmel-aic.c | ||
irq-bcm2835.c | ||
irq-bcm2836.c | ||
irq-bcm6345-l1.c | ||
irq-bcm7038-l1.c | ||
irq-bcm7120-l2.c | ||
irq-brcmstb-l2.c | ||
irq-clps711x.c | ||
irq-crossbar.c | ||
irq-digicolor.c | ||
irq-dw-apb-ictl.c | ||
irq-eznps.c | ||
irq-ftintc010.c | ||
irq-gic-common.c | ||
irq-gic-common.h | ||
irq-gic-pm.c | ||
irq-gic-realview.c | ||
irq-gic-v2m.c | ||
irq-gic-v3-its-fsl-mc-msi.c | ||
irq-gic-v3-its-pci-msi.c | ||
irq-gic-v3-its-platform-msi.c | ||
irq-gic-v3-its.c | ||
irq-gic-v3-mbi.c | ||
irq-gic-v3.c | ||
irq-gic-v4.c | ||
irq-gic.c | ||
irq-goldfish-pic.c | ||
irq-hip04.c | ||
irq-i8259.c | ||
irq-imgpdc.c | ||
irq-imx-gpcv2.c | ||
irq-ingenic.c | ||
irq-jcore-aic.c | ||
irq-keystone.c | ||
irq-lpc32xx.c | ||
irq-ls-scfg-msi.c | ||
irq-mbigen.c | ||
irq-meson-gpio.c | ||
irq-mips-cpu.c | ||
irq-mips-gic.c | ||
irq-mmp.c | ||
irq-mscc-ocelot.c | ||
irq-mtk-cirq.c | ||
irq-mtk-sysirq.c | ||
irq-mvebu-gicp.c | ||
irq-mvebu-icu.c | ||
irq-mvebu-odmi.c | ||
irq-mvebu-pic.c | ||
irq-mxs.c | ||
irq-nvic.c | ||
irq-omap-intc.c | ||
irq-ompic.c | ||
irq-or1k-pic.c | ||
irq-orion.c | ||
irq-partition-percpu.c | ||
irq-pic32-evic.c | ||
irq-renesas-h8s.c | ||
irq-renesas-h8300h.c | ||
irq-renesas-intc-irqpin.c | ||
irq-renesas-irqc.c | ||
irq-s3c24xx.c | ||
irq-sa11x0.c | ||
irq-sifive-plic.c | ||
irq-sirfsoc.c | ||
irq-sni-exiu.c | ||
irq-st.c | ||
irq-stm32-exti.c | ||
irq-sun4i.c | ||
irq-sunxi-nmi.c | ||
irq-tango.c | ||
irq-tb10x.c | ||
irq-tegra.c | ||
irq-ts4800.c | ||
irq-uniphier-aidet.c | ||
irq-versatile-fpga.c | ||
irq-vf610-mscm-ir.c | ||
irq-vic.c | ||
irq-vt8500.c | ||
irq-xilinx-intc.c | ||
irq-xtensa-mx.c | ||
irq-xtensa-pic.c | ||
irq-zevio.c | ||
irqchip.c | ||
Kconfig | ||
Makefile | ||
qcom-irq-combiner.c | ||
qcom-pdc.c | ||
spear-shirq.c |