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482b05dd53
Replaced check_user_space() + __check_access_register with the new check_space(). The old functions made wrong assumptions about kernel and user space when the kernel and user address spaces are switched (kernel in home space, user in primary/secondary space). Secondly the user process can switch to the accress register mode if it is running in primary or secondary mode. In addition it can load an arbitrary value to the access registers. If any other value than 0 for primary space or 1 for secondary space is loaded and memory is accessed using the base register related to the access register, the program should be terminated with a SIGSEGV. To achieve that the DUALD pointer in the DUCT and the PSALD pointer in the PASTE need to point to an array of 8 invalid access-list entries to get a ALEN-translation exception if an invalid alet is used. Signed-off-by: Gerald Schaefer <geraldsc@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
189 lines
4.8 KiB
ArmAsm
189 lines
4.8 KiB
ArmAsm
/*
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* arch/s390/kernel/head31.S
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*
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* Copyright (C) IBM Corp. 2005,2006
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*
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* Author(s): Hartmut Penner <hp@de.ibm.com>
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* Martin Schwidefsky <schwidefsky@de.ibm.com>
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* Rob van der Heij <rvdhei@iae.nl>
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* Heiko Carstens <heiko.carstens@de.ibm.com>
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*
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*/
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#
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# startup-code at 0x10000, running in absolute addressing mode
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# this is called either by the ipl loader or directly by PSW restart
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# or linload or SALIPL
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#
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.org 0x10000
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startup:basr %r13,0 # get base
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.LPG0: l %r13,0f-.LPG0(%r13)
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b 0(%r13)
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0: .long startup_continue
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#
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# params at 10400 (setup.h)
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#
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.org PARMAREA
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.long 0,0 # IPL_DEVICE
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.long 0,0 # INITRD_START
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.long 0,0 # INITRD_SIZE
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.org COMMAND_LINE
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.byte "root=/dev/ram0 ro"
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.byte 0
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.org 0x11000
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startup_continue:
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basr %r13,0 # get base
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.LPG1: mvi __LC_AR_MODE_ID,0 # set ESA flag (mode 0)
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lctl %c0,%c15,.Lctl-.LPG1(%r13) # load control registers
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l %r12,.Lparmaddr-.LPG1(%r13) # pointer to parameter area
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# move IPL device to lowcore
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mvc __LC_IPLDEV(4),IPL_DEVICE-PARMAREA(%r12)
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#
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# Setup stack
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#
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l %r15,.Linittu-.LPG1(%r13)
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mvc __LC_CURRENT(4),__TI_task(%r15)
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ahi %r15,1<<(PAGE_SHIFT+THREAD_ORDER) # init_task_union+THREAD_SIZE
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st %r15,__LC_KERNEL_STACK # set end of kernel stack
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ahi %r15,-96
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xc __SF_BACKCHAIN(4,%r15),__SF_BACKCHAIN(%r15) # clear backchain
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#
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# Save ipl parameters, clear bss memory, initialize storage key for kernel pages,
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# and create a kernel NSS if the SAVESYS= parm is defined
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#
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l %r14,.Lstartup_init-.LPG1(%r13)
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basr %r14,%r14
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l %r12,.Lmflags-.LPG1(%r13) # get address of machine_flags
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#
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# find out if we have an IEEE fpu
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#
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mvc __LC_PGM_NEW_PSW(8),.Lpcfpu-.LPG1(%r13)
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efpc %r0,0 # test IEEE extract fpc instruction
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oi 3(%r12),2 # set IEEE fpu flag
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.Lchkfpu:
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#
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# find out if we have the CSP instruction
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#
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mvc __LC_PGM_NEW_PSW(8),.Lpccsp-.LPG1(%r13)
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la %r0,0
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lr %r1,%r0
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la %r2,4
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csp %r0,%r2 # Test CSP instruction
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oi 3(%r12),8 # set CSP flag
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.Lchkcsp:
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#
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# find out if we have the MVPG instruction
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#
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mvc __LC_PGM_NEW_PSW(8),.Lpcmvpg-.LPG1(%r13)
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sr %r0,%r0
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la %r1,0
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la %r2,0
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mvpg %r1,%r2 # Test CSP instruction
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oi 3(%r12),16 # set MVPG flag
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.Lchkmvpg:
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#
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# find out if we have the IDTE instruction
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#
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mvc __LC_PGM_NEW_PSW(8),.Lpcidte-.LPG1(%r13)
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.long 0xb2b10000 # store facility list
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tm 0xc8,0x08 # check bit for clearing-by-ASCE
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bno .Lchkidte-.LPG1(%r13)
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lhi %r1,2094
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lhi %r2,0
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.long 0xb98e2001
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oi 3(%r12),0x80 # set IDTE flag
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.Lchkidte:
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#
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# find out if the diag 0x9c is available
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#
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mvc __LC_PGM_NEW_PSW(8),.Lpcdiag9c-.LPG1(%r13)
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stap __LC_CPUID+4 # store cpu address
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lh %r1,__LC_CPUID+4
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diag %r1,0,0x9c # test diag 0x9c
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oi 2(%r12),1 # set diag9c flag
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.Lchkdiag9c:
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lpsw .Lentry-.LPG1(13) # jump to _stext in primary-space,
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# virtual and never return ...
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.align 8
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.Lentry:.long 0x00080000,0x80000000 + _stext
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.Lctl: .long 0x04b50002 # cr0: various things
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.long 0 # cr1: primary space segment table
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.long .Lduct # cr2: dispatchable unit control table
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.long 0 # cr3: instruction authorization
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.long 0 # cr4: instruction authorization
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.long .Lduct # cr5: primary-aste origin
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.long 0 # cr6: I/O interrupts
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.long 0 # cr7: secondary space segment table
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.long 0 # cr8: access registers translation
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.long 0 # cr9: tracing off
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.long 0 # cr10: tracing off
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.long 0 # cr11: tracing off
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.long 0 # cr12: tracing off
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.long 0 # cr13: home space segment table
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.long 0xc0000000 # cr14: machine check handling off
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.long 0 # cr15: linkage stack operations
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.Lpcfpu:.long 0x00080000,0x80000000 + .Lchkfpu
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.Lpccsp:.long 0x00080000,0x80000000 + .Lchkcsp
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.Lpcmvpg:.long 0x00080000,0x80000000 + .Lchkmvpg
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.Lpcidte:.long 0x00080000,0x80000000 + .Lchkidte
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.Lpcdiag9c:.long 0x00080000,0x80000000 + .Lchkdiag9c
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.Lmchunk:.long memory_chunk
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.Lmflags:.long machine_flags
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.Lbss_bgn: .long __bss_start
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.Lbss_end: .long _end
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.Lparmaddr: .long PARMAREA
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.Linittu: .long init_thread_union
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.Lstartup_init:
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.long startup_init
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.align 64
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.Lduct: .long 0,0,0,0,.Lduald,0,0,0
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.long 0,0,0,0,0,0,0,0
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.align 128
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.Lduald:.rept 8
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.long 0x80000000,0,0,0 # invalid access-list entries
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.endr
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.org 0x12000
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.globl _ehead
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_ehead:
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#ifdef CONFIG_SHARED_KERNEL
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.org 0x100000
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#endif
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#
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# startup-code, running in absolute addressing mode
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#
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.globl _stext
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_stext: basr %r13,0 # get base
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.LPG3:
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# check control registers
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stctl %c0,%c15,0(%r15)
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oi 2(%r15),0x40 # enable sigp emergency signal
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oi 0(%r15),0x10 # switch on low address protection
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lctl %c0,%c15,0(%r15)
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#
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lam 0,15,.Laregs-.LPG3(%r13) # load access regs needed by uaccess
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l %r14,.Lstart-.LPG3(%r13)
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basr %r14,%r14 # call start_kernel
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#
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# We returned from start_kernel ?!? PANIK
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#
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basr %r13,0
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lpsw .Ldw-.(%r13) # load disabled wait psw
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#
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.align 8
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.Ldw: .long 0x000a0000,0x00000000
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.Lstart:.long start_kernel
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.Laregs:.long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
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