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e35735b9a5
Unroll clear_page 8 times. A simple microbenchmark which
allocates and frees a zeroed page:
for (i = 0; i < iterations; i++) {
unsigned long p = __get_free_page(GFP_KERNEL | __GFP_ZERO);
free_page(p);
}
improves 20% on POWER8.
This assumes cacheline sizes won't grow beyond 512 bytes or
page sizes wont drop below 1kB, which is unlikely, but we could
add a runtime check during early init if it makes people nervous.
Michael found that some versions of gcc produce quite bad code
(all multiplies), so we give gcc a hand by using shifts and adds.
Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
188 lines
5.0 KiB
C
188 lines
5.0 KiB
C
#ifndef _ASM_POWERPC_PAGE_64_H
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#define _ASM_POWERPC_PAGE_64_H
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/*
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* Copyright (C) 2001 PPC64 Team, IBM Corp
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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/*
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* We always define HW_PAGE_SHIFT to 12 as use of 64K pages remains Linux
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* specific, every notion of page number shared with the firmware, TCEs,
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* iommu, etc... still uses a page size of 4K.
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*/
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#define HW_PAGE_SHIFT 12
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#define HW_PAGE_SIZE (ASM_CONST(1) << HW_PAGE_SHIFT)
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#define HW_PAGE_MASK (~(HW_PAGE_SIZE-1))
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/*
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* PAGE_FACTOR is the number of bits factor between PAGE_SHIFT and
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* HW_PAGE_SHIFT, that is 4K pages.
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*/
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#define PAGE_FACTOR (PAGE_SHIFT - HW_PAGE_SHIFT)
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/* Segment size; normal 256M segments */
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#define SID_SHIFT 28
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#define SID_MASK ASM_CONST(0xfffffffff)
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#define ESID_MASK 0xfffffffff0000000UL
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#define GET_ESID(x) (((x) >> SID_SHIFT) & SID_MASK)
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/* 1T segments */
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#define SID_SHIFT_1T 40
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#define SID_MASK_1T 0xffffffUL
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#define ESID_MASK_1T 0xffffff0000000000UL
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#define GET_ESID_1T(x) (((x) >> SID_SHIFT_1T) & SID_MASK_1T)
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#ifndef __ASSEMBLY__
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#include <asm/cache.h>
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typedef unsigned long pte_basic_t;
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static inline void clear_page(void *addr)
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{
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unsigned long iterations;
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unsigned long onex, twox, fourx, eightx;
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iterations = ppc64_caches.dlines_per_page / 8;
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/*
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* Some verisions of gcc use multiply instructions to
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* calculate the offsets so lets give it a hand to
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* do better.
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*/
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onex = ppc64_caches.dline_size;
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twox = onex << 1;
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fourx = onex << 2;
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eightx = onex << 3;
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asm volatile(
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"mtctr %1 # clear_page\n\
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.balign 16\n\
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1: dcbz 0,%0\n\
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dcbz %3,%0\n\
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dcbz %4,%0\n\
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dcbz %5,%0\n\
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dcbz %6,%0\n\
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dcbz %7,%0\n\
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dcbz %8,%0\n\
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dcbz %9,%0\n\
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add %0,%0,%10\n\
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bdnz+ 1b"
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: "=&r" (addr)
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: "r" (iterations), "0" (addr), "b" (onex), "b" (twox),
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"b" (twox+onex), "b" (fourx), "b" (fourx+onex),
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"b" (twox+fourx), "b" (eightx-onex), "r" (eightx)
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: "ctr", "memory");
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}
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extern void copy_page(void *to, void *from);
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/* Log 2 of page table size */
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extern u64 ppc64_pft_size;
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#endif /* __ASSEMBLY__ */
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#ifdef CONFIG_PPC_MM_SLICES
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#define SLICE_LOW_SHIFT 28
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#define SLICE_HIGH_SHIFT 40
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#define SLICE_LOW_TOP (0x100000000ul)
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#define SLICE_NUM_LOW (SLICE_LOW_TOP >> SLICE_LOW_SHIFT)
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#define SLICE_NUM_HIGH (PGTABLE_RANGE >> SLICE_HIGH_SHIFT)
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#define GET_LOW_SLICE_INDEX(addr) ((addr) >> SLICE_LOW_SHIFT)
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#define GET_HIGH_SLICE_INDEX(addr) ((addr) >> SLICE_HIGH_SHIFT)
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/*
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* 1 bit per slice and we have one slice per 1TB
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* Right now we support only 64TB.
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* IF we change this we will have to change the type
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* of high_slices
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*/
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#define SLICE_MASK_SIZE 8
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#ifndef __ASSEMBLY__
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struct slice_mask {
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u16 low_slices;
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u64 high_slices;
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};
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struct mm_struct;
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extern unsigned long slice_get_unmapped_area(unsigned long addr,
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unsigned long len,
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unsigned long flags,
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unsigned int psize,
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int topdown);
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extern unsigned int get_slice_psize(struct mm_struct *mm,
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unsigned long addr);
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extern void slice_set_user_psize(struct mm_struct *mm, unsigned int psize);
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extern void slice_set_range_psize(struct mm_struct *mm, unsigned long start,
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unsigned long len, unsigned int psize);
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#define slice_mm_new_context(mm) ((mm)->context.id == MMU_NO_CONTEXT)
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#endif /* __ASSEMBLY__ */
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#else
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#define slice_init()
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#ifdef CONFIG_PPC_STD_MMU_64
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#define get_slice_psize(mm, addr) ((mm)->context.user_psize)
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#define slice_set_user_psize(mm, psize) \
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do { \
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(mm)->context.user_psize = (psize); \
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(mm)->context.sllp = SLB_VSID_USER | mmu_psize_defs[(psize)].sllp; \
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} while (0)
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#else /* CONFIG_PPC_STD_MMU_64 */
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#ifdef CONFIG_PPC_64K_PAGES
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#define get_slice_psize(mm, addr) MMU_PAGE_64K
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#else /* CONFIG_PPC_64K_PAGES */
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#define get_slice_psize(mm, addr) MMU_PAGE_4K
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#endif /* !CONFIG_PPC_64K_PAGES */
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#define slice_set_user_psize(mm, psize) do { BUG(); } while(0)
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#endif /* !CONFIG_PPC_STD_MMU_64 */
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#define slice_set_range_psize(mm, start, len, psize) \
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slice_set_user_psize((mm), (psize))
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#define slice_mm_new_context(mm) 1
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#endif /* CONFIG_PPC_MM_SLICES */
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#ifdef CONFIG_HUGETLB_PAGE
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#ifdef CONFIG_PPC_MM_SLICES
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#define HAVE_ARCH_HUGETLB_UNMAPPED_AREA
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#endif
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#endif /* !CONFIG_HUGETLB_PAGE */
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#define VM_DATA_DEFAULT_FLAGS \
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(is_32bit_task() ? \
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VM_DATA_DEFAULT_FLAGS32 : VM_DATA_DEFAULT_FLAGS64)
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/*
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* This is the default if a program doesn't have a PT_GNU_STACK
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* program header entry. The PPC64 ELF ABI has a non executable stack
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* stack by default, so in the absence of a PT_GNU_STACK program header
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* we turn execute permission off.
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*/
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#define VM_STACK_DEFAULT_FLAGS32 (VM_READ | VM_WRITE | VM_EXEC | \
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VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
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#define VM_STACK_DEFAULT_FLAGS64 (VM_READ | VM_WRITE | \
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VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
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#define VM_STACK_DEFAULT_FLAGS \
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(is_32bit_task() ? \
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VM_STACK_DEFAULT_FLAGS32 : VM_STACK_DEFAULT_FLAGS64)
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#include <asm-generic/getorder.h>
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#endif /* _ASM_POWERPC_PAGE_64_H */
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