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ARCv2 based HS38 cores are weakly ordered and thus explicit barriers for kernel proper. SMP barrier is provided by DMB instruction which also guarantees local barrier hence used as backend of smp_*mb() as well as *mb() APIs Also hookup barriers into MMIO accessors to avoid ordering issues in IO Cc: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
49 lines
1.5 KiB
C
49 lines
1.5 KiB
C
/*
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* Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_BARRIER_H
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#define __ASM_BARRIER_H
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#ifdef CONFIG_ISA_ARCV2
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/*
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* ARCv2 based HS38 cores are in-order issue, but still weakly ordered
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* due to micro-arch buffering/queuing of load/store, cache hit vs. miss ...
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*
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* Explicit barrier provided by DMB instruction
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* - Operand supports fine grained load/store/load+store semantics
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* - Ensures that selected memory operation issued before it will complete
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* before any subsequent memory operation of same type
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* - DMB guarantees SMP as well as local barrier semantics
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* (asm-generic/barrier.h ensures sane smp_*mb if not defined here, i.e.
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* UP: barrier(), SMP: smp_*mb == *mb)
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* - DSYNC provides DMB+completion_of_cache_bpu_maintenance_ops hence not needed
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* in the general case. Plus it only provides full barrier.
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*/
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#define mb() asm volatile("dmb 3\n" : : : "memory")
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#define rmb() asm volatile("dmb 1\n" : : : "memory")
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#define wmb() asm volatile("dmb 2\n" : : : "memory")
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#endif
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#ifdef CONFIG_ISA_ARCOMPACT
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/*
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* ARCompact based cores (ARC700) only have SYNC instruction which is super
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* heavy weight as it flushes the pipeline as well.
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* There are no real SMP implementations of such cores.
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*/
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#define mb() asm volatile("sync\n" : : : "memory")
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#endif
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#include <asm-generic/barrier.h>
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#endif
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