Guo Ren ae76f635d4 csky: Optimize arch_sync_dma_for_cpu/device with dma_inv_range ... DMA_FROM_DEVICE only need to read dma data of memory into CPU cache, so there is no need to clear cache before. Also clear + inv for DMA_FROM_DEVICE won't cause problem, because the memory range for dma won't be touched by software during dma working. Changes for V2: - Remove clr cache and ignore the DMA_TO_DEVICE in _for_cpu. - Change inv to wbinv cache with DMA_FROM_DEVICE in _for_device. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Cc: Arnd Bergmann <arnd@arndb.de>		2019-08-06 15:15:34 +08:00
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asid.c	csky: Add new asid lib code from arm	2019-07-19 14:21:36 +08:00
cachev1.c	csky: Optimize arch_sync_dma_for_cpu/device with dma_inv_range	2019-08-06 15:15:34 +08:00
cachev2.c	csky: Optimize arch_sync_dma_for_cpu/device with dma_inv_range	2019-08-06 15:15:34 +08:00
context.c	csky: Use generic asid algorithm to implement switch_mm	2019-07-19 14:21:36 +08:00
dma-mapping.c	csky: Optimize arch_sync_dma_for_cpu/device with dma_inv_range	2019-08-06 15:15:34 +08:00
fault.c	signal: Remove the task parameter from force_sig_fault	2019-05-29 09:31:43 -05:00
highmem.c	treewide: add checks for the return value of memblock_alloc*()	2019-03-12 10:04:02 -07:00
init.c	csky: Revert mmu ASID mechanism	2019-07-19 14:21:36 +08:00
ioremap.c	csky: Fixup dma_alloc_coherent with PAGE_SO attribute	2019-07-31 11:05:25 +08:00
Makefile	csky: Use generic asid algorithm to implement switch_mm	2019-07-19 14:21:36 +08:00
syscache.c	csky: Cache and TLB routines	2018-10-25 23:36:19 +08:00
tlb.c	csky: Improve tlb operation with help of asid	2019-07-19 14:21:36 +08:00