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b6338bdc83
The new fncpy API is better suited* for copying some
code to SRAM at runtime. This patch changes the ad-hoc
code to the more generic fncpy API.
*: 1. fncpy ensures that the thumb mode bit is propagated,
2. fncpy provides the security of type safety between the
original function and the sram function pointer.
Tested OK on OMAP3 in low power modes (RET/OFF)
using omap2plus_defconfig with !CONFIG_THUMB2_KERNEL.
Compile tested on OMAP1/2 using omap1_defconfig.
Boot tested on OMAP1 & OMAP2
Tested OK with suspend/resume on OMAP2420/n810
Boots fine on osk5912 and n800
Signed-off-by: Jean Pihet <j-pihet@ti.com>
Acked-by: Kevin Hilman <khilman@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Reviewed-by: Dave Martin <dave.martin@linaro.org>
Tested-by: Kevin Hilman <khilman@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
59 lines
1.5 KiB
ArmAsm
59 lines
1.5 KiB
ArmAsm
/*
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* linux/arch/arm/plat-omap/sram-fn.S
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*
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* Functions that need to be run in internal SRAM
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <mach/io.h>
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#include <mach/hardware.h>
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.text
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/*
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* Reprograms ULPD and CKCTL.
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*/
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.align 3
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ENTRY(omap1_sram_reprogram_clock)
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stmfd sp!, {r0 - r12, lr} @ save registers on stack
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mov r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0xff000000
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orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x00ff0000
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orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x0000ff00
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mov r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0xff000000
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orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x00ff0000
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orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x0000ff00
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tst r0, #1 << 4 @ want lock mode?
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beq newck @ nope
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bic r0, r0, #1 << 4 @ else clear lock bit
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strh r0, [r2] @ set dpll into bypass mode
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orr r0, r0, #1 << 4 @ set lock bit again
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newck:
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strh r1, [r3] @ write new ckctl value
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strh r0, [r2] @ write new dpll value
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mov r4, #0x0700 @ let the clocks settle
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orr r4, r4, #0x00ff
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delay: sub r4, r4, #1
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cmp r4, #0
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bne delay
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lock: ldrh r4, [r2], #0 @ read back dpll value
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tst r0, #1 << 4 @ want lock mode?
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beq out @ nope
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tst r4, #1 << 0 @ dpll rate locked?
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beq lock @ try again
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out:
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ldmfd sp!, {r0 - r12, pc} @ restore regs and return
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ENTRY(omap1_sram_reprogram_clock_sz)
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.word . - omap1_sram_reprogram_clock
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