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94b0522ab7
* 's5p-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: SAMSUNG: DMA Cleanup as per sparse ARM: SAMSUNG: Check NULL return from irq_alloc_generic_chip
90 lines
2.6 KiB
C
90 lines
2.6 KiB
C
/* arch/arm/plat-samsung/irq-uart.c
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* originally part of arch/arm/plat-s3c64xx/irq.c
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* Samsung- UART Interrupt handling
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/serial_core.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <mach/map.h>
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#include <plat/irq-uart.h>
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#include <plat/regs-serial.h>
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#include <plat/cpu.h>
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/* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3]
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* are consecutive when looking up the interrupt in the demux routines.
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*/
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static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc)
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{
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struct s3c_uart_irq *uirq = desc->irq_data.handler_data;
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u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP);
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int base = uirq->base_irq;
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if (pend & (1 << 0))
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generic_handle_irq(base);
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if (pend & (1 << 1))
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generic_handle_irq(base + 1);
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if (pend & (1 << 2))
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generic_handle_irq(base + 2);
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if (pend & (1 << 3))
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generic_handle_irq(base + 3);
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}
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static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq)
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{
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void __iomem *reg_base = uirq->regs;
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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/* mask all interrupts at the start. */
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__raw_writel(0xf, reg_base + S3C64XX_UINTM);
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gc = irq_alloc_generic_chip("s3c-uart", 1, uirq->base_irq, reg_base,
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handle_level_irq);
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if (!gc) {
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pr_err("%s: irq_alloc_generic_chip for IRQ %u failed\n",
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__func__, uirq->base_irq);
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return;
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}
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ct = gc->chip_types;
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ct->chip.irq_ack = irq_gc_ack_set_bit;
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ct->chip.irq_mask = irq_gc_mask_set_bit;
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ct->chip.irq_unmask = irq_gc_mask_clr_bit;
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ct->regs.ack = S3C64XX_UINTP;
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ct->regs.mask = S3C64XX_UINTM;
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irq_setup_generic_chip(gc, IRQ_MSK(4), IRQ_GC_INIT_MASK_CACHE,
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IRQ_NOREQUEST | IRQ_NOPROBE, 0);
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irq_set_handler_data(uirq->parent_irq, uirq);
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irq_set_chained_handler(uirq->parent_irq, s3c_irq_demux_uart);
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}
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/**
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* s3c_init_uart_irqs() - initialise UART IRQs and the necessary demuxing
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* @irq: The interrupt data for registering
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* @nr_irqs: The number of interrupt descriptions in @irq.
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*
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* Register the UART interrupts specified by @irq including the demuxing
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* routines. This supports the S3C6400 and newer style of devices.
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*/
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void __init s3c_init_uart_irqs(struct s3c_uart_irq *irq, unsigned int nr_irqs)
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{
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for (; nr_irqs > 0; nr_irqs--, irq++)
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s3c_init_uart_irq(irq);
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}
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