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e6b5be2be4
Here's the set of driver core patches for 3.19-rc1. They are dominated by the removal of the .owner field in platform drivers. They touch a lot of files, but they are "simple" changes, just removing a line in a structure. Other than that, a few minor driver core and debugfs changes. There are some ath9k patches coming in through this tree that have been acked by the wireless maintainers as they relied on the debugfs changes. Everything has been in linux-next for a while. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iEYEABECAAYFAlSOD20ACgkQMUfUDdst+ylLPACg2QrW1oHhdTMT9WI8jihlHVRM 53kAoLeteByQ3iVwWurwwseRPiWa8+MI =OVRS -----END PGP SIGNATURE----- Merge tag 'driver-core-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core Pull driver core update from Greg KH: "Here's the set of driver core patches for 3.19-rc1. They are dominated by the removal of the .owner field in platform drivers. They touch a lot of files, but they are "simple" changes, just removing a line in a structure. Other than that, a few minor driver core and debugfs changes. There are some ath9k patches coming in through this tree that have been acked by the wireless maintainers as they relied on the debugfs changes. Everything has been in linux-next for a while" * tag 'driver-core-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core: (324 commits) Revert "ath: ath9k: use debugfs_create_devm_seqfile() helper for seq_file entries" fs: debugfs: add forward declaration for struct device type firmware class: Deletion of an unnecessary check before the function call "vunmap" firmware loader: fix hung task warning dump devcoredump: provide a one-way disable function device: Add dev_<level>_once variants ath: ath9k: use debugfs_create_devm_seqfile() helper for seq_file entries ath: use seq_file api for ath9k debugfs files debugfs: add helper function to create device related seq_file drivers/base: cacheinfo: remove noisy error boot message Revert "core: platform: add warning if driver has no owner" drivers: base: support cpu cache information interface to userspace via sysfs drivers: base: add cpu_device_create to support per-cpu devices topology: replace custom attribute macros with standard DEVICE_ATTR* cpumask: factor out show_cpumap into separate helper function driver core: Fix unbalanced device reference in drivers_probe driver core: fix race with userland in device_add() sysfs/kernfs: make read requests on pre-alloc files use the buffer. sysfs/kernfs: allow attributes to request write buffer be pre-allocated. fs: sysfs: return EGBIG on write if offset is larger than file size ...
585 lines
14 KiB
C
585 lines
14 KiB
C
/*
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* Freescale MXS SPI master driver
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*
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* Copyright 2012 DENX Software Engineering, GmbH.
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* Copyright 2012 Freescale Semiconductor, Inc.
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* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
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*
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* Rework and transition to new API by:
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* Marek Vasut <marex@denx.de>
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*
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* Based on previous attempt by:
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* Fabio Estevam <fabio.estevam@freescale.com>
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*
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* Based on code from U-Boot bootloader by:
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* Marek Vasut <marex@denx.de>
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*
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* Based on spi-stmp.c, which is:
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* Author: Dmitry Pervushin <dimka@embeddedalley.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/ioport.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_gpio.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmaengine.h>
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#include <linux/highmem.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/completion.h>
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#include <linux/gpio.h>
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#include <linux/regulator/consumer.h>
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#include <linux/module.h>
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#include <linux/stmp_device.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/mxs-spi.h>
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#define DRIVER_NAME "mxs-spi"
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/* Use 10S timeout for very long transfers, it should suffice. */
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#define SSP_TIMEOUT 10000
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#define SG_MAXLEN 0xff00
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/*
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* Flags for txrx functions. More efficient that using an argument register for
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* each one.
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*/
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#define TXRX_WRITE (1<<0) /* This is a write */
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#define TXRX_DEASSERT_CS (1<<1) /* De-assert CS at end of txrx */
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struct mxs_spi {
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struct mxs_ssp ssp;
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struct completion c;
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unsigned int sck; /* Rate requested (vs actual) */
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};
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static int mxs_spi_setup_transfer(struct spi_device *dev,
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const struct spi_transfer *t)
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{
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struct mxs_spi *spi = spi_master_get_devdata(dev->master);
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struct mxs_ssp *ssp = &spi->ssp;
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const unsigned int hz = min(dev->max_speed_hz, t->speed_hz);
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if (hz == 0) {
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dev_err(&dev->dev, "SPI clock rate of zero not allowed\n");
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return -EINVAL;
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}
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if (hz != spi->sck) {
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mxs_ssp_set_clk_rate(ssp, hz);
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/*
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* Save requested rate, hz, rather than the actual rate,
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* ssp->clk_rate. Otherwise we would set the rate every transfer
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* when the actual rate is not quite the same as requested rate.
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*/
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spi->sck = hz;
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/*
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* Perhaps we should return an error if the actual clock is
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* nowhere close to what was requested?
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*/
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}
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writel(BM_SSP_CTRL0_LOCK_CS,
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ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
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writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) |
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BF_SSP_CTRL1_WORD_LENGTH(BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) |
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((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) |
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((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0),
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ssp->base + HW_SSP_CTRL1(ssp));
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writel(0x0, ssp->base + HW_SSP_CMD0);
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writel(0x0, ssp->base + HW_SSP_CMD1);
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return 0;
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}
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static u32 mxs_spi_cs_to_reg(unsigned cs)
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{
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u32 select = 0;
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/*
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* i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0
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*
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* The bits BM_SSP_CTRL0_WAIT_FOR_CMD and BM_SSP_CTRL0_WAIT_FOR_IRQ
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* in HW_SSP_CTRL0 register do have multiple usage, please refer to
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* the datasheet for further details. In SPI mode, they are used to
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* toggle the chip-select lines (nCS pins).
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*/
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if (cs & 1)
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select |= BM_SSP_CTRL0_WAIT_FOR_CMD;
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if (cs & 2)
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select |= BM_SSP_CTRL0_WAIT_FOR_IRQ;
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return select;
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}
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static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set)
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{
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const unsigned long timeout = jiffies + msecs_to_jiffies(SSP_TIMEOUT);
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struct mxs_ssp *ssp = &spi->ssp;
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u32 reg;
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do {
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reg = readl_relaxed(ssp->base + offset);
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if (!set)
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reg = ~reg;
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reg &= mask;
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if (reg == mask)
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return 0;
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} while (time_before(jiffies, timeout));
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return -ETIMEDOUT;
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}
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static void mxs_ssp_dma_irq_callback(void *param)
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{
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struct mxs_spi *spi = param;
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complete(&spi->c);
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}
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static irqreturn_t mxs_ssp_irq_handler(int irq, void *dev_id)
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{
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struct mxs_ssp *ssp = dev_id;
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dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n",
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__func__, __LINE__,
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readl(ssp->base + HW_SSP_CTRL1(ssp)),
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readl(ssp->base + HW_SSP_STATUS(ssp)));
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return IRQ_HANDLED;
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}
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static int mxs_spi_txrx_dma(struct mxs_spi *spi,
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unsigned char *buf, int len,
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unsigned int flags)
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{
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struct mxs_ssp *ssp = &spi->ssp;
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struct dma_async_tx_descriptor *desc = NULL;
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const bool vmalloced_buf = is_vmalloc_addr(buf);
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const int desc_len = vmalloced_buf ? PAGE_SIZE : SG_MAXLEN;
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const int sgs = DIV_ROUND_UP(len, desc_len);
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int sg_count;
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int min, ret;
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u32 ctrl0;
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struct page *vm_page;
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struct {
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u32 pio[4];
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struct scatterlist sg;
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} *dma_xfer;
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if (!len)
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return -EINVAL;
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dma_xfer = kcalloc(sgs, sizeof(*dma_xfer), GFP_KERNEL);
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if (!dma_xfer)
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return -ENOMEM;
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reinit_completion(&spi->c);
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/* Chip select was already programmed into CTRL0 */
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ctrl0 = readl(ssp->base + HW_SSP_CTRL0);
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ctrl0 &= ~(BM_SSP_CTRL0_XFER_COUNT | BM_SSP_CTRL0_IGNORE_CRC |
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BM_SSP_CTRL0_READ);
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ctrl0 |= BM_SSP_CTRL0_DATA_XFER;
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if (!(flags & TXRX_WRITE))
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ctrl0 |= BM_SSP_CTRL0_READ;
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/* Queue the DMA data transfer. */
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for (sg_count = 0; sg_count < sgs; sg_count++) {
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/* Prepare the transfer descriptor. */
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min = min(len, desc_len);
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/*
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* De-assert CS on last segment if flag is set (i.e., no more
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* transfers will follow)
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*/
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if ((sg_count + 1 == sgs) && (flags & TXRX_DEASSERT_CS))
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ctrl0 |= BM_SSP_CTRL0_IGNORE_CRC;
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if (ssp->devid == IMX23_SSP) {
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ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
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ctrl0 |= min;
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}
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dma_xfer[sg_count].pio[0] = ctrl0;
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dma_xfer[sg_count].pio[3] = min;
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if (vmalloced_buf) {
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vm_page = vmalloc_to_page(buf);
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if (!vm_page) {
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ret = -ENOMEM;
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goto err_vmalloc;
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}
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sg_init_table(&dma_xfer[sg_count].sg, 1);
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sg_set_page(&dma_xfer[sg_count].sg, vm_page,
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min, offset_in_page(buf));
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} else {
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sg_init_one(&dma_xfer[sg_count].sg, buf, min);
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}
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ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
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(flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
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len -= min;
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buf += min;
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/* Queue the PIO register write transfer. */
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desc = dmaengine_prep_slave_sg(ssp->dmach,
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(struct scatterlist *)dma_xfer[sg_count].pio,
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(ssp->devid == IMX23_SSP) ? 1 : 4,
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DMA_TRANS_NONE,
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sg_count ? DMA_PREP_INTERRUPT : 0);
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if (!desc) {
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dev_err(ssp->dev,
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"Failed to get PIO reg. write descriptor.\n");
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ret = -EINVAL;
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goto err_mapped;
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}
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desc = dmaengine_prep_slave_sg(ssp->dmach,
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&dma_xfer[sg_count].sg, 1,
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(flags & TXRX_WRITE) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!desc) {
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dev_err(ssp->dev,
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"Failed to get DMA data write descriptor.\n");
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ret = -EINVAL;
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goto err_mapped;
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}
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}
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/*
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* The last descriptor must have this callback,
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* to finish the DMA transaction.
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*/
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desc->callback = mxs_ssp_dma_irq_callback;
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desc->callback_param = spi;
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/* Start the transfer. */
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dmaengine_submit(desc);
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dma_async_issue_pending(ssp->dmach);
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ret = wait_for_completion_timeout(&spi->c,
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msecs_to_jiffies(SSP_TIMEOUT));
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if (!ret) {
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dev_err(ssp->dev, "DMA transfer timeout\n");
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ret = -ETIMEDOUT;
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dmaengine_terminate_all(ssp->dmach);
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goto err_vmalloc;
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}
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ret = 0;
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err_vmalloc:
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while (--sg_count >= 0) {
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err_mapped:
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dma_unmap_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
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(flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
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}
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kfree(dma_xfer);
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return ret;
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}
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static int mxs_spi_txrx_pio(struct mxs_spi *spi,
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unsigned char *buf, int len,
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unsigned int flags)
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{
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struct mxs_ssp *ssp = &spi->ssp;
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writel(BM_SSP_CTRL0_IGNORE_CRC,
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ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
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while (len--) {
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if (len == 0 && (flags & TXRX_DEASSERT_CS))
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writel(BM_SSP_CTRL0_IGNORE_CRC,
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ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
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if (ssp->devid == IMX23_SSP) {
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writel(BM_SSP_CTRL0_XFER_COUNT,
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ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
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writel(1,
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ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
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} else {
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writel(1, ssp->base + HW_SSP_XFER_SIZE);
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}
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if (flags & TXRX_WRITE)
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writel(BM_SSP_CTRL0_READ,
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ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
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else
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writel(BM_SSP_CTRL0_READ,
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ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
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writel(BM_SSP_CTRL0_RUN,
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ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
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if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 1))
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return -ETIMEDOUT;
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if (flags & TXRX_WRITE)
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writel(*buf, ssp->base + HW_SSP_DATA(ssp));
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writel(BM_SSP_CTRL0_DATA_XFER,
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ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
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if (!(flags & TXRX_WRITE)) {
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if (mxs_ssp_wait(spi, HW_SSP_STATUS(ssp),
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BM_SSP_STATUS_FIFO_EMPTY, 0))
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return -ETIMEDOUT;
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*buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff);
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}
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if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 0))
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return -ETIMEDOUT;
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buf++;
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}
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if (len <= 0)
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return 0;
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return -ETIMEDOUT;
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}
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static int mxs_spi_transfer_one(struct spi_master *master,
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struct spi_message *m)
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{
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struct mxs_spi *spi = spi_master_get_devdata(master);
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struct mxs_ssp *ssp = &spi->ssp;
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struct spi_transfer *t;
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unsigned int flag;
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int status = 0;
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/* Program CS register bits here, it will be used for all transfers. */
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writel(BM_SSP_CTRL0_WAIT_FOR_CMD | BM_SSP_CTRL0_WAIT_FOR_IRQ,
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ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
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writel(mxs_spi_cs_to_reg(m->spi->chip_select),
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ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
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list_for_each_entry(t, &m->transfers, transfer_list) {
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status = mxs_spi_setup_transfer(m->spi, t);
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if (status)
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break;
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/* De-assert on last transfer, inverted by cs_change flag */
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flag = (&t->transfer_list == m->transfers.prev) ^ t->cs_change ?
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TXRX_DEASSERT_CS : 0;
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/*
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* Small blocks can be transfered via PIO.
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* Measured by empiric means:
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*
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* dd if=/dev/mtdblock0 of=/dev/null bs=1024k count=1
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*
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* DMA only: 2.164808 seconds, 473.0KB/s
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* Combined: 1.676276 seconds, 610.9KB/s
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*/
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if (t->len < 32) {
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writel(BM_SSP_CTRL1_DMA_ENABLE,
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ssp->base + HW_SSP_CTRL1(ssp) +
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STMP_OFFSET_REG_CLR);
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if (t->tx_buf)
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status = mxs_spi_txrx_pio(spi,
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(void *)t->tx_buf,
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t->len, flag | TXRX_WRITE);
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if (t->rx_buf)
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status = mxs_spi_txrx_pio(spi,
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t->rx_buf, t->len,
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flag);
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} else {
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writel(BM_SSP_CTRL1_DMA_ENABLE,
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ssp->base + HW_SSP_CTRL1(ssp) +
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STMP_OFFSET_REG_SET);
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if (t->tx_buf)
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status = mxs_spi_txrx_dma(spi,
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(void *)t->tx_buf, t->len,
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flag | TXRX_WRITE);
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if (t->rx_buf)
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status = mxs_spi_txrx_dma(spi,
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t->rx_buf, t->len,
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flag);
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}
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if (status) {
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stmp_reset_block(ssp->base);
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break;
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}
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m->actual_length += t->len;
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}
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m->status = status;
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spi_finalize_current_message(master);
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return status;
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}
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static const struct of_device_id mxs_spi_dt_ids[] = {
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{ .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, },
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{ .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, mxs_spi_dt_ids);
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static int mxs_spi_probe(struct platform_device *pdev)
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{
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const struct of_device_id *of_id =
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of_match_device(mxs_spi_dt_ids, &pdev->dev);
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struct device_node *np = pdev->dev.of_node;
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struct spi_master *master;
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struct mxs_spi *spi;
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struct mxs_ssp *ssp;
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struct resource *iores;
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struct clk *clk;
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void __iomem *base;
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int devid, clk_freq;
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int ret = 0, irq_err;
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/*
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* Default clock speed for the SPI core. 160MHz seems to
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* work reasonably well with most SPI flashes, so use this
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* as a default. Override with "clock-frequency" DT prop.
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*/
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const int clk_freq_default = 160000000;
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iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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irq_err = platform_get_irq(pdev, 0);
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if (irq_err < 0)
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return irq_err;
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base = devm_ioremap_resource(&pdev->dev, iores);
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if (IS_ERR(base))
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return PTR_ERR(base);
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clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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devid = (enum mxs_ssp_id) of_id->data;
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ret = of_property_read_u32(np, "clock-frequency",
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&clk_freq);
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if (ret)
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clk_freq = clk_freq_default;
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master = spi_alloc_master(&pdev->dev, sizeof(*spi));
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if (!master)
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return -ENOMEM;
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master->transfer_one_message = mxs_spi_transfer_one;
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master->bits_per_word_mask = SPI_BPW_MASK(8);
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master->mode_bits = SPI_CPOL | SPI_CPHA;
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master->num_chipselect = 3;
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master->dev.of_node = np;
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master->flags = SPI_MASTER_HALF_DUPLEX;
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spi = spi_master_get_devdata(master);
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ssp = &spi->ssp;
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ssp->dev = &pdev->dev;
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ssp->clk = clk;
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ssp->base = base;
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ssp->devid = devid;
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init_completion(&spi->c);
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ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0,
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dev_name(&pdev->dev), ssp);
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if (ret)
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goto out_master_free;
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ssp->dmach = dma_request_slave_channel(&pdev->dev, "rx-tx");
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if (!ssp->dmach) {
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dev_err(ssp->dev, "Failed to request DMA\n");
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ret = -ENODEV;
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goto out_master_free;
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}
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ret = clk_prepare_enable(ssp->clk);
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if (ret)
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goto out_dma_release;
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clk_set_rate(ssp->clk, clk_freq);
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ret = stmp_reset_block(ssp->base);
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if (ret)
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goto out_disable_clk;
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platform_set_drvdata(pdev, master);
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ret = devm_spi_register_master(&pdev->dev, master);
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if (ret) {
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dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret);
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goto out_disable_clk;
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}
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return 0;
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out_disable_clk:
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clk_disable_unprepare(ssp->clk);
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out_dma_release:
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dma_release_channel(ssp->dmach);
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out_master_free:
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spi_master_put(master);
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return ret;
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}
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static int mxs_spi_remove(struct platform_device *pdev)
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{
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struct spi_master *master;
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struct mxs_spi *spi;
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struct mxs_ssp *ssp;
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master = platform_get_drvdata(pdev);
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spi = spi_master_get_devdata(master);
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ssp = &spi->ssp;
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clk_disable_unprepare(ssp->clk);
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dma_release_channel(ssp->dmach);
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return 0;
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}
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static struct platform_driver mxs_spi_driver = {
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.probe = mxs_spi_probe,
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.remove = mxs_spi_remove,
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.driver = {
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.name = DRIVER_NAME,
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.of_match_table = mxs_spi_dt_ids,
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},
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};
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module_platform_driver(mxs_spi_driver);
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MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
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MODULE_DESCRIPTION("MXS SPI master driver");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:mxs-spi");
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