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e6b5be2be4
Here's the set of driver core patches for 3.19-rc1. They are dominated by the removal of the .owner field in platform drivers. They touch a lot of files, but they are "simple" changes, just removing a line in a structure. Other than that, a few minor driver core and debugfs changes. There are some ath9k patches coming in through this tree that have been acked by the wireless maintainers as they relied on the debugfs changes. Everything has been in linux-next for a while. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iEYEABECAAYFAlSOD20ACgkQMUfUDdst+ylLPACg2QrW1oHhdTMT9WI8jihlHVRM 53kAoLeteByQ3iVwWurwwseRPiWa8+MI =OVRS -----END PGP SIGNATURE----- Merge tag 'driver-core-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core Pull driver core update from Greg KH: "Here's the set of driver core patches for 3.19-rc1. They are dominated by the removal of the .owner field in platform drivers. They touch a lot of files, but they are "simple" changes, just removing a line in a structure. Other than that, a few minor driver core and debugfs changes. There are some ath9k patches coming in through this tree that have been acked by the wireless maintainers as they relied on the debugfs changes. Everything has been in linux-next for a while" * tag 'driver-core-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core: (324 commits) Revert "ath: ath9k: use debugfs_create_devm_seqfile() helper for seq_file entries" fs: debugfs: add forward declaration for struct device type firmware class: Deletion of an unnecessary check before the function call "vunmap" firmware loader: fix hung task warning dump devcoredump: provide a one-way disable function device: Add dev_<level>_once variants ath: ath9k: use debugfs_create_devm_seqfile() helper for seq_file entries ath: use seq_file api for ath9k debugfs files debugfs: add helper function to create device related seq_file drivers/base: cacheinfo: remove noisy error boot message Revert "core: platform: add warning if driver has no owner" drivers: base: support cpu cache information interface to userspace via sysfs drivers: base: add cpu_device_create to support per-cpu devices topology: replace custom attribute macros with standard DEVICE_ATTR* cpumask: factor out show_cpumap into separate helper function driver core: Fix unbalanced device reference in drivers_probe driver core: fix race with userland in device_add() sysfs/kernfs: make read requests on pre-alloc files use the buffer. sysfs/kernfs: allow attributes to request write buffer be pre-allocated. fs: sysfs: return EGBIG on write if offset is larger than file size ...
864 lines
20 KiB
C
864 lines
20 KiB
C
/*
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* Freescale eSPI controller driver.
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*
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* Copyright 2010 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/fsl_devices.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include <linux/mm.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/spi/spi.h>
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#include <sysdev/fsl_soc.h>
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#include "spi-fsl-lib.h"
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/* eSPI Controller registers */
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struct fsl_espi_reg {
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__be32 mode; /* 0x000 - eSPI mode register */
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__be32 event; /* 0x004 - eSPI event register */
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__be32 mask; /* 0x008 - eSPI mask register */
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__be32 command; /* 0x00c - eSPI command register */
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__be32 transmit; /* 0x010 - eSPI transmit FIFO access register*/
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__be32 receive; /* 0x014 - eSPI receive FIFO access register*/
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u8 res[8]; /* 0x018 - 0x01c reserved */
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__be32 csmode[4]; /* 0x020 - 0x02c eSPI cs mode register */
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};
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struct fsl_espi_transfer {
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const void *tx_buf;
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void *rx_buf;
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unsigned len;
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unsigned n_tx;
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unsigned n_rx;
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unsigned actual_length;
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int status;
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};
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/* eSPI Controller mode register definitions */
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#define SPMODE_ENABLE (1 << 31)
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#define SPMODE_LOOP (1 << 30)
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#define SPMODE_TXTHR(x) ((x) << 8)
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#define SPMODE_RXTHR(x) ((x) << 0)
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/* eSPI Controller CS mode register definitions */
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#define CSMODE_CI_INACTIVEHIGH (1 << 31)
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#define CSMODE_CP_BEGIN_EDGECLK (1 << 30)
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#define CSMODE_REV (1 << 29)
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#define CSMODE_DIV16 (1 << 28)
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#define CSMODE_PM(x) ((x) << 24)
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#define CSMODE_POL_1 (1 << 20)
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#define CSMODE_LEN(x) ((x) << 16)
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#define CSMODE_BEF(x) ((x) << 12)
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#define CSMODE_AFT(x) ((x) << 8)
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#define CSMODE_CG(x) ((x) << 3)
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/* Default mode/csmode for eSPI controller */
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#define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(3))
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#define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \
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| CSMODE_AFT(0) | CSMODE_CG(1))
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/* SPIE register values */
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#define SPIE_NE 0x00000200 /* Not empty */
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#define SPIE_NF 0x00000100 /* Not full */
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/* SPIM register values */
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#define SPIM_NE 0x00000200 /* Not empty */
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#define SPIM_NF 0x00000100 /* Not full */
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#define SPIE_RXCNT(reg) ((reg >> 24) & 0x3F)
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#define SPIE_TXCNT(reg) ((reg >> 16) & 0x3F)
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/* SPCOM register values */
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#define SPCOM_CS(x) ((x) << 30)
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#define SPCOM_TRANLEN(x) ((x) << 0)
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#define SPCOM_TRANLEN_MAX 0xFFFF /* Max transaction length */
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static void fsl_espi_change_mode(struct spi_device *spi)
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{
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struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
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struct spi_mpc8xxx_cs *cs = spi->controller_state;
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struct fsl_espi_reg *reg_base = mspi->reg_base;
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__be32 __iomem *mode = ®_base->csmode[spi->chip_select];
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__be32 __iomem *espi_mode = ®_base->mode;
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u32 tmp;
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unsigned long flags;
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/* Turn off IRQs locally to minimize time that SPI is disabled. */
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local_irq_save(flags);
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/* Turn off SPI unit prior changing mode */
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tmp = mpc8xxx_spi_read_reg(espi_mode);
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mpc8xxx_spi_write_reg(espi_mode, tmp & ~SPMODE_ENABLE);
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mpc8xxx_spi_write_reg(mode, cs->hw_mode);
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mpc8xxx_spi_write_reg(espi_mode, tmp);
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local_irq_restore(flags);
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}
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static u32 fsl_espi_tx_buf_lsb(struct mpc8xxx_spi *mpc8xxx_spi)
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{
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u32 data;
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u16 data_h;
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u16 data_l;
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const u32 *tx = mpc8xxx_spi->tx;
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if (!tx)
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return 0;
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data = *tx++ << mpc8xxx_spi->tx_shift;
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data_l = data & 0xffff;
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data_h = (data >> 16) & 0xffff;
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swab16s(&data_l);
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swab16s(&data_h);
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data = data_h | data_l;
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mpc8xxx_spi->tx = tx;
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return data;
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}
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static int fsl_espi_setup_transfer(struct spi_device *spi,
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struct spi_transfer *t)
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{
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struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
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int bits_per_word = 0;
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u8 pm;
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u32 hz = 0;
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struct spi_mpc8xxx_cs *cs = spi->controller_state;
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if (t) {
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bits_per_word = t->bits_per_word;
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hz = t->speed_hz;
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}
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/* spi_transfer level calls that work per-word */
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if (!bits_per_word)
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bits_per_word = spi->bits_per_word;
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if (!hz)
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hz = spi->max_speed_hz;
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cs->rx_shift = 0;
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cs->tx_shift = 0;
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cs->get_rx = mpc8xxx_spi_rx_buf_u32;
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cs->get_tx = mpc8xxx_spi_tx_buf_u32;
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if (bits_per_word <= 8) {
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cs->rx_shift = 8 - bits_per_word;
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} else {
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cs->rx_shift = 16 - bits_per_word;
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if (spi->mode & SPI_LSB_FIRST)
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cs->get_tx = fsl_espi_tx_buf_lsb;
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}
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mpc8xxx_spi->rx_shift = cs->rx_shift;
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mpc8xxx_spi->tx_shift = cs->tx_shift;
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mpc8xxx_spi->get_rx = cs->get_rx;
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mpc8xxx_spi->get_tx = cs->get_tx;
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bits_per_word = bits_per_word - 1;
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/* mask out bits we are going to set */
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cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF));
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cs->hw_mode |= CSMODE_LEN(bits_per_word);
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if ((mpc8xxx_spi->spibrg / hz) > 64) {
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cs->hw_mode |= CSMODE_DIV16;
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pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4);
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WARN_ONCE(pm > 33, "%s: Requested speed is too low: %d Hz. "
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"Will use %d Hz instead.\n", dev_name(&spi->dev),
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hz, mpc8xxx_spi->spibrg / (4 * 16 * (32 + 1)));
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if (pm > 33)
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pm = 33;
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} else {
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pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4);
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}
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if (pm)
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pm--;
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if (pm < 2)
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pm = 2;
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cs->hw_mode |= CSMODE_PM(pm);
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fsl_espi_change_mode(spi);
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return 0;
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}
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static int fsl_espi_cpu_bufs(struct mpc8xxx_spi *mspi, struct spi_transfer *t,
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unsigned int len)
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{
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u32 word;
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struct fsl_espi_reg *reg_base = mspi->reg_base;
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mspi->count = len;
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/* enable rx ints */
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mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE);
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/* transmit word */
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word = mspi->get_tx(mspi);
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mpc8xxx_spi_write_reg(®_base->transmit, word);
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return 0;
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}
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static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t)
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{
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struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
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struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
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unsigned int len = t->len;
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int ret;
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mpc8xxx_spi->len = t->len;
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len = roundup(len, 4) / 4;
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mpc8xxx_spi->tx = t->tx_buf;
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mpc8xxx_spi->rx = t->rx_buf;
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reinit_completion(&mpc8xxx_spi->done);
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/* Set SPCOM[CS] and SPCOM[TRANLEN] field */
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if ((t->len - 1) > SPCOM_TRANLEN_MAX) {
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dev_err(mpc8xxx_spi->dev, "Transaction length (%d)"
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" beyond the SPCOM[TRANLEN] field\n", t->len);
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return -EINVAL;
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}
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mpc8xxx_spi_write_reg(®_base->command,
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(SPCOM_CS(spi->chip_select) | SPCOM_TRANLEN(t->len - 1)));
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ret = fsl_espi_cpu_bufs(mpc8xxx_spi, t, len);
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if (ret)
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return ret;
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wait_for_completion(&mpc8xxx_spi->done);
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/* disable rx ints */
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mpc8xxx_spi_write_reg(®_base->mask, 0);
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return mpc8xxx_spi->count;
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}
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static inline void fsl_espi_addr2cmd(unsigned int addr, u8 *cmd)
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{
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if (cmd) {
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cmd[1] = (u8)(addr >> 16);
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cmd[2] = (u8)(addr >> 8);
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cmd[3] = (u8)(addr >> 0);
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}
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}
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static inline unsigned int fsl_espi_cmd2addr(u8 *cmd)
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{
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if (cmd)
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return cmd[1] << 16 | cmd[2] << 8 | cmd[3] << 0;
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return 0;
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}
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static void fsl_espi_do_trans(struct spi_message *m,
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struct fsl_espi_transfer *tr)
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{
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struct spi_device *spi = m->spi;
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struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
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struct fsl_espi_transfer *espi_trans = tr;
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struct spi_message message;
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struct spi_transfer *t, *first, trans;
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int status = 0;
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spi_message_init(&message);
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memset(&trans, 0, sizeof(trans));
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first = list_first_entry(&m->transfers, struct spi_transfer,
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transfer_list);
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list_for_each_entry(t, &m->transfers, transfer_list) {
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if ((first->bits_per_word != t->bits_per_word) ||
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(first->speed_hz != t->speed_hz)) {
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espi_trans->status = -EINVAL;
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dev_err(mspi->dev,
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"bits_per_word/speed_hz should be same for the same SPI transfer\n");
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return;
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}
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trans.speed_hz = t->speed_hz;
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trans.bits_per_word = t->bits_per_word;
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trans.delay_usecs = max(first->delay_usecs, t->delay_usecs);
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}
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trans.len = espi_trans->len;
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trans.tx_buf = espi_trans->tx_buf;
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trans.rx_buf = espi_trans->rx_buf;
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spi_message_add_tail(&trans, &message);
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list_for_each_entry(t, &message.transfers, transfer_list) {
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if (t->bits_per_word || t->speed_hz) {
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status = -EINVAL;
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status = fsl_espi_setup_transfer(spi, t);
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if (status < 0)
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break;
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}
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if (t->len)
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status = fsl_espi_bufs(spi, t);
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if (status) {
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status = -EMSGSIZE;
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break;
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}
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if (t->delay_usecs)
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udelay(t->delay_usecs);
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}
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espi_trans->status = status;
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fsl_espi_setup_transfer(spi, NULL);
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}
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static void fsl_espi_cmd_trans(struct spi_message *m,
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struct fsl_espi_transfer *trans, u8 *rx_buff)
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{
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struct spi_transfer *t;
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u8 *local_buf;
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int i = 0;
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struct fsl_espi_transfer *espi_trans = trans;
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local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL);
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if (!local_buf) {
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espi_trans->status = -ENOMEM;
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return;
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}
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list_for_each_entry(t, &m->transfers, transfer_list) {
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if (t->tx_buf) {
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memcpy(local_buf + i, t->tx_buf, t->len);
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i += t->len;
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}
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}
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espi_trans->tx_buf = local_buf;
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espi_trans->rx_buf = local_buf;
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fsl_espi_do_trans(m, espi_trans);
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espi_trans->actual_length = espi_trans->len;
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kfree(local_buf);
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}
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static void fsl_espi_rw_trans(struct spi_message *m,
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struct fsl_espi_transfer *trans, u8 *rx_buff)
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{
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struct fsl_espi_transfer *espi_trans = trans;
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unsigned int n_tx = espi_trans->n_tx;
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unsigned int n_rx = espi_trans->n_rx;
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struct spi_transfer *t;
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u8 *local_buf;
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u8 *rx_buf = rx_buff;
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unsigned int trans_len;
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unsigned int addr;
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int i, pos, loop;
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local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL);
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if (!local_buf) {
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espi_trans->status = -ENOMEM;
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return;
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}
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for (pos = 0, loop = 0; pos < n_rx; pos += trans_len, loop++) {
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trans_len = n_rx - pos;
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if (trans_len > SPCOM_TRANLEN_MAX - n_tx)
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trans_len = SPCOM_TRANLEN_MAX - n_tx;
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i = 0;
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list_for_each_entry(t, &m->transfers, transfer_list) {
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if (t->tx_buf) {
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memcpy(local_buf + i, t->tx_buf, t->len);
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i += t->len;
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}
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}
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if (pos > 0) {
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addr = fsl_espi_cmd2addr(local_buf);
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addr += pos;
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fsl_espi_addr2cmd(addr, local_buf);
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}
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espi_trans->n_tx = n_tx;
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espi_trans->n_rx = trans_len;
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espi_trans->len = trans_len + n_tx;
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espi_trans->tx_buf = local_buf;
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espi_trans->rx_buf = local_buf;
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fsl_espi_do_trans(m, espi_trans);
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memcpy(rx_buf + pos, espi_trans->rx_buf + n_tx, trans_len);
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if (loop > 0)
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espi_trans->actual_length += espi_trans->len - n_tx;
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else
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espi_trans->actual_length += espi_trans->len;
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}
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kfree(local_buf);
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}
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static int fsl_espi_do_one_msg(struct spi_master *master,
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struct spi_message *m)
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{
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struct spi_transfer *t;
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u8 *rx_buf = NULL;
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unsigned int n_tx = 0;
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unsigned int n_rx = 0;
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struct fsl_espi_transfer espi_trans;
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list_for_each_entry(t, &m->transfers, transfer_list) {
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if (t->tx_buf)
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n_tx += t->len;
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if (t->rx_buf) {
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n_rx += t->len;
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rx_buf = t->rx_buf;
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}
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}
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espi_trans.n_tx = n_tx;
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espi_trans.n_rx = n_rx;
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espi_trans.len = n_tx + n_rx;
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espi_trans.actual_length = 0;
|
|
espi_trans.status = 0;
|
|
|
|
if (!rx_buf)
|
|
fsl_espi_cmd_trans(m, &espi_trans, NULL);
|
|
else
|
|
fsl_espi_rw_trans(m, &espi_trans, rx_buf);
|
|
|
|
m->actual_length = espi_trans.actual_length;
|
|
m->status = espi_trans.status;
|
|
spi_finalize_current_message(master);
|
|
return 0;
|
|
}
|
|
|
|
static int fsl_espi_setup(struct spi_device *spi)
|
|
{
|
|
struct mpc8xxx_spi *mpc8xxx_spi;
|
|
struct fsl_espi_reg *reg_base;
|
|
int retval;
|
|
u32 hw_mode;
|
|
u32 loop_mode;
|
|
struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
|
|
|
|
if (!spi->max_speed_hz)
|
|
return -EINVAL;
|
|
|
|
if (!cs) {
|
|
cs = kzalloc(sizeof(*cs), GFP_KERNEL);
|
|
if (!cs)
|
|
return -ENOMEM;
|
|
spi_set_ctldata(spi, cs);
|
|
}
|
|
|
|
mpc8xxx_spi = spi_master_get_devdata(spi->master);
|
|
reg_base = mpc8xxx_spi->reg_base;
|
|
|
|
hw_mode = cs->hw_mode; /* Save original settings */
|
|
cs->hw_mode = mpc8xxx_spi_read_reg(
|
|
®_base->csmode[spi->chip_select]);
|
|
/* mask out bits we are going to set */
|
|
cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH
|
|
| CSMODE_REV);
|
|
|
|
if (spi->mode & SPI_CPHA)
|
|
cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK;
|
|
if (spi->mode & SPI_CPOL)
|
|
cs->hw_mode |= CSMODE_CI_INACTIVEHIGH;
|
|
if (!(spi->mode & SPI_LSB_FIRST))
|
|
cs->hw_mode |= CSMODE_REV;
|
|
|
|
/* Handle the loop mode */
|
|
loop_mode = mpc8xxx_spi_read_reg(®_base->mode);
|
|
loop_mode &= ~SPMODE_LOOP;
|
|
if (spi->mode & SPI_LOOP)
|
|
loop_mode |= SPMODE_LOOP;
|
|
mpc8xxx_spi_write_reg(®_base->mode, loop_mode);
|
|
|
|
retval = fsl_espi_setup_transfer(spi, NULL);
|
|
if (retval < 0) {
|
|
cs->hw_mode = hw_mode; /* Restore settings */
|
|
return retval;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static void fsl_espi_cleanup(struct spi_device *spi)
|
|
{
|
|
struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
|
|
|
|
kfree(cs);
|
|
spi_set_ctldata(spi, NULL);
|
|
}
|
|
|
|
void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
|
|
{
|
|
struct fsl_espi_reg *reg_base = mspi->reg_base;
|
|
|
|
/* We need handle RX first */
|
|
if (events & SPIE_NE) {
|
|
u32 rx_data, tmp;
|
|
u8 rx_data_8;
|
|
|
|
/* Spin until RX is done */
|
|
while (SPIE_RXCNT(events) < min(4, mspi->len)) {
|
|
cpu_relax();
|
|
events = mpc8xxx_spi_read_reg(®_base->event);
|
|
}
|
|
|
|
if (mspi->len >= 4) {
|
|
rx_data = mpc8xxx_spi_read_reg(®_base->receive);
|
|
} else {
|
|
tmp = mspi->len;
|
|
rx_data = 0;
|
|
while (tmp--) {
|
|
rx_data_8 = in_8((u8 *)®_base->receive);
|
|
rx_data |= (rx_data_8 << (tmp * 8));
|
|
}
|
|
|
|
rx_data <<= (4 - mspi->len) * 8;
|
|
}
|
|
|
|
mspi->len -= 4;
|
|
|
|
if (mspi->rx)
|
|
mspi->get_rx(rx_data, mspi);
|
|
}
|
|
|
|
if (!(events & SPIE_NF)) {
|
|
int ret;
|
|
|
|
/* spin until TX is done */
|
|
ret = spin_event_timeout(((events = mpc8xxx_spi_read_reg(
|
|
®_base->event)) & SPIE_NF) == 0, 1000, 0);
|
|
if (!ret) {
|
|
dev_err(mspi->dev, "tired waiting for SPIE_NF\n");
|
|
return;
|
|
}
|
|
}
|
|
|
|
/* Clear the events */
|
|
mpc8xxx_spi_write_reg(®_base->event, events);
|
|
|
|
mspi->count -= 1;
|
|
if (mspi->count) {
|
|
u32 word = mspi->get_tx(mspi);
|
|
|
|
mpc8xxx_spi_write_reg(®_base->transmit, word);
|
|
} else {
|
|
complete(&mspi->done);
|
|
}
|
|
}
|
|
|
|
static irqreturn_t fsl_espi_irq(s32 irq, void *context_data)
|
|
{
|
|
struct mpc8xxx_spi *mspi = context_data;
|
|
struct fsl_espi_reg *reg_base = mspi->reg_base;
|
|
irqreturn_t ret = IRQ_NONE;
|
|
u32 events;
|
|
|
|
/* Get interrupt events(tx/rx) */
|
|
events = mpc8xxx_spi_read_reg(®_base->event);
|
|
if (events)
|
|
ret = IRQ_HANDLED;
|
|
|
|
dev_vdbg(mspi->dev, "%s: events %x\n", __func__, events);
|
|
|
|
fsl_espi_cpu_irq(mspi, events);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void fsl_espi_remove(struct mpc8xxx_spi *mspi)
|
|
{
|
|
iounmap(mspi->reg_base);
|
|
}
|
|
|
|
static int fsl_espi_suspend(struct spi_master *master)
|
|
{
|
|
struct mpc8xxx_spi *mpc8xxx_spi;
|
|
struct fsl_espi_reg *reg_base;
|
|
u32 regval;
|
|
|
|
mpc8xxx_spi = spi_master_get_devdata(master);
|
|
reg_base = mpc8xxx_spi->reg_base;
|
|
|
|
regval = mpc8xxx_spi_read_reg(®_base->mode);
|
|
regval &= ~SPMODE_ENABLE;
|
|
mpc8xxx_spi_write_reg(®_base->mode, regval);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int fsl_espi_resume(struct spi_master *master)
|
|
{
|
|
struct mpc8xxx_spi *mpc8xxx_spi;
|
|
struct fsl_espi_reg *reg_base;
|
|
u32 regval;
|
|
|
|
mpc8xxx_spi = spi_master_get_devdata(master);
|
|
reg_base = mpc8xxx_spi->reg_base;
|
|
|
|
regval = mpc8xxx_spi_read_reg(®_base->mode);
|
|
regval |= SPMODE_ENABLE;
|
|
mpc8xxx_spi_write_reg(®_base->mode, regval);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct spi_master * fsl_espi_probe(struct device *dev,
|
|
struct resource *mem, unsigned int irq)
|
|
{
|
|
struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
|
|
struct spi_master *master;
|
|
struct mpc8xxx_spi *mpc8xxx_spi;
|
|
struct fsl_espi_reg *reg_base;
|
|
struct device_node *nc;
|
|
const __be32 *prop;
|
|
u32 regval, csmode;
|
|
int i, len, ret = 0;
|
|
|
|
master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
|
|
if (!master) {
|
|
ret = -ENOMEM;
|
|
goto err;
|
|
}
|
|
|
|
dev_set_drvdata(dev, master);
|
|
|
|
mpc8xxx_spi_probe(dev, mem, irq);
|
|
|
|
master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
|
|
master->setup = fsl_espi_setup;
|
|
master->cleanup = fsl_espi_cleanup;
|
|
master->transfer_one_message = fsl_espi_do_one_msg;
|
|
master->prepare_transfer_hardware = fsl_espi_resume;
|
|
master->unprepare_transfer_hardware = fsl_espi_suspend;
|
|
|
|
mpc8xxx_spi = spi_master_get_devdata(master);
|
|
mpc8xxx_spi->spi_remove = fsl_espi_remove;
|
|
|
|
mpc8xxx_spi->reg_base = ioremap(mem->start, resource_size(mem));
|
|
if (!mpc8xxx_spi->reg_base) {
|
|
ret = -ENOMEM;
|
|
goto err_probe;
|
|
}
|
|
|
|
reg_base = mpc8xxx_spi->reg_base;
|
|
|
|
/* Register for SPI Interrupt */
|
|
ret = request_irq(mpc8xxx_spi->irq, fsl_espi_irq,
|
|
0, "fsl_espi", mpc8xxx_spi);
|
|
if (ret)
|
|
goto free_irq;
|
|
|
|
if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
|
|
mpc8xxx_spi->rx_shift = 16;
|
|
mpc8xxx_spi->tx_shift = 24;
|
|
}
|
|
|
|
/* SPI controller initializations */
|
|
mpc8xxx_spi_write_reg(®_base->mode, 0);
|
|
mpc8xxx_spi_write_reg(®_base->mask, 0);
|
|
mpc8xxx_spi_write_reg(®_base->command, 0);
|
|
mpc8xxx_spi_write_reg(®_base->event, 0xffffffff);
|
|
|
|
/* Init eSPI CS mode register */
|
|
for_each_available_child_of_node(master->dev.of_node, nc) {
|
|
/* get chip select */
|
|
prop = of_get_property(nc, "reg", &len);
|
|
if (!prop || len < sizeof(*prop))
|
|
continue;
|
|
i = be32_to_cpup(prop);
|
|
if (i < 0 || i >= pdata->max_chipselect)
|
|
continue;
|
|
|
|
csmode = CSMODE_INIT_VAL;
|
|
/* check if CSBEF is set in device tree */
|
|
prop = of_get_property(nc, "fsl,csbef", &len);
|
|
if (prop && len >= sizeof(*prop)) {
|
|
csmode &= ~(CSMODE_BEF(0xf));
|
|
csmode |= CSMODE_BEF(be32_to_cpup(prop));
|
|
}
|
|
/* check if CSAFT is set in device tree */
|
|
prop = of_get_property(nc, "fsl,csaft", &len);
|
|
if (prop && len >= sizeof(*prop)) {
|
|
csmode &= ~(CSMODE_AFT(0xf));
|
|
csmode |= CSMODE_AFT(be32_to_cpup(prop));
|
|
}
|
|
mpc8xxx_spi_write_reg(®_base->csmode[i], csmode);
|
|
|
|
dev_info(dev, "cs=%d, init_csmode=0x%x\n", i, csmode);
|
|
}
|
|
|
|
/* Enable SPI interface */
|
|
regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
|
|
|
|
mpc8xxx_spi_write_reg(®_base->mode, regval);
|
|
|
|
ret = spi_register_master(master);
|
|
if (ret < 0)
|
|
goto unreg_master;
|
|
|
|
dev_info(dev, "at 0x%p (irq = %d)\n", reg_base, mpc8xxx_spi->irq);
|
|
|
|
return master;
|
|
|
|
unreg_master:
|
|
free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
|
|
free_irq:
|
|
iounmap(mpc8xxx_spi->reg_base);
|
|
err_probe:
|
|
spi_master_put(master);
|
|
err:
|
|
return ERR_PTR(ret);
|
|
}
|
|
|
|
static int of_fsl_espi_get_chipselects(struct device *dev)
|
|
{
|
|
struct device_node *np = dev->of_node;
|
|
struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
|
|
const u32 *prop;
|
|
int len;
|
|
|
|
prop = of_get_property(np, "fsl,espi-num-chipselects", &len);
|
|
if (!prop || len < sizeof(*prop)) {
|
|
dev_err(dev, "No 'fsl,espi-num-chipselects' property\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
pdata->max_chipselect = *prop;
|
|
pdata->cs_control = NULL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int of_fsl_espi_probe(struct platform_device *ofdev)
|
|
{
|
|
struct device *dev = &ofdev->dev;
|
|
struct device_node *np = ofdev->dev.of_node;
|
|
struct spi_master *master;
|
|
struct resource mem;
|
|
unsigned int irq;
|
|
int ret = -ENOMEM;
|
|
|
|
ret = of_mpc8xxx_spi_probe(ofdev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = of_fsl_espi_get_chipselects(dev);
|
|
if (ret)
|
|
goto err;
|
|
|
|
ret = of_address_to_resource(np, 0, &mem);
|
|
if (ret)
|
|
goto err;
|
|
|
|
irq = irq_of_parse_and_map(np, 0);
|
|
if (!irq) {
|
|
ret = -EINVAL;
|
|
goto err;
|
|
}
|
|
|
|
master = fsl_espi_probe(dev, &mem, irq);
|
|
if (IS_ERR(master)) {
|
|
ret = PTR_ERR(master);
|
|
goto err;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err:
|
|
return ret;
|
|
}
|
|
|
|
static int of_fsl_espi_remove(struct platform_device *dev)
|
|
{
|
|
return mpc8xxx_spi_remove(&dev->dev);
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int of_fsl_espi_suspend(struct device *dev)
|
|
{
|
|
struct spi_master *master = dev_get_drvdata(dev);
|
|
int ret;
|
|
|
|
ret = spi_master_suspend(master);
|
|
if (ret) {
|
|
dev_warn(dev, "cannot suspend master\n");
|
|
return ret;
|
|
}
|
|
|
|
return fsl_espi_suspend(master);
|
|
}
|
|
|
|
static int of_fsl_espi_resume(struct device *dev)
|
|
{
|
|
struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
|
|
struct spi_master *master = dev_get_drvdata(dev);
|
|
struct mpc8xxx_spi *mpc8xxx_spi;
|
|
struct fsl_espi_reg *reg_base;
|
|
u32 regval;
|
|
int i;
|
|
|
|
mpc8xxx_spi = spi_master_get_devdata(master);
|
|
reg_base = mpc8xxx_spi->reg_base;
|
|
|
|
/* SPI controller initializations */
|
|
mpc8xxx_spi_write_reg(®_base->mode, 0);
|
|
mpc8xxx_spi_write_reg(®_base->mask, 0);
|
|
mpc8xxx_spi_write_reg(®_base->command, 0);
|
|
mpc8xxx_spi_write_reg(®_base->event, 0xffffffff);
|
|
|
|
/* Init eSPI CS mode register */
|
|
for (i = 0; i < pdata->max_chipselect; i++)
|
|
mpc8xxx_spi_write_reg(®_base->csmode[i], CSMODE_INIT_VAL);
|
|
|
|
/* Enable SPI interface */
|
|
regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
|
|
|
|
mpc8xxx_spi_write_reg(®_base->mode, regval);
|
|
|
|
return spi_master_resume(master);
|
|
}
|
|
#endif /* CONFIG_PM_SLEEP */
|
|
|
|
static const struct dev_pm_ops espi_pm = {
|
|
SET_SYSTEM_SLEEP_PM_OPS(of_fsl_espi_suspend, of_fsl_espi_resume)
|
|
};
|
|
|
|
static const struct of_device_id of_fsl_espi_match[] = {
|
|
{ .compatible = "fsl,mpc8536-espi" },
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, of_fsl_espi_match);
|
|
|
|
static struct platform_driver fsl_espi_driver = {
|
|
.driver = {
|
|
.name = "fsl_espi",
|
|
.of_match_table = of_fsl_espi_match,
|
|
.pm = &espi_pm,
|
|
},
|
|
.probe = of_fsl_espi_probe,
|
|
.remove = of_fsl_espi_remove,
|
|
};
|
|
module_platform_driver(fsl_espi_driver);
|
|
|
|
MODULE_AUTHOR("Mingkai Hu");
|
|
MODULE_DESCRIPTION("Enhanced Freescale SPI Driver");
|
|
MODULE_LICENSE("GPL");
|