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14ac00e033
A platform_driver does not need to set an owner, it will be populated by the driver core. Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
408 lines
11 KiB
C
408 lines
11 KiB
C
/*
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* Driver for Broadcom BCM2835 SPI Controllers
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*
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* Copyright (C) 2012 Chris Boot
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* Copyright (C) 2013 Stephen Warren
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*
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* This driver is inspired by:
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* spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
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* spi-atmel.c, Copyright (C) 2006 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_device.h>
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#include <linux/spi/spi.h>
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/* SPI register offsets */
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#define BCM2835_SPI_CS 0x00
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#define BCM2835_SPI_FIFO 0x04
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#define BCM2835_SPI_CLK 0x08
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#define BCM2835_SPI_DLEN 0x0c
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#define BCM2835_SPI_LTOH 0x10
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#define BCM2835_SPI_DC 0x14
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/* Bitfields in CS */
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#define BCM2835_SPI_CS_LEN_LONG 0x02000000
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#define BCM2835_SPI_CS_DMA_LEN 0x01000000
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#define BCM2835_SPI_CS_CSPOL2 0x00800000
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#define BCM2835_SPI_CS_CSPOL1 0x00400000
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#define BCM2835_SPI_CS_CSPOL0 0x00200000
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#define BCM2835_SPI_CS_RXF 0x00100000
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#define BCM2835_SPI_CS_RXR 0x00080000
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#define BCM2835_SPI_CS_TXD 0x00040000
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#define BCM2835_SPI_CS_RXD 0x00020000
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#define BCM2835_SPI_CS_DONE 0x00010000
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#define BCM2835_SPI_CS_LEN 0x00002000
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#define BCM2835_SPI_CS_REN 0x00001000
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#define BCM2835_SPI_CS_ADCS 0x00000800
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#define BCM2835_SPI_CS_INTR 0x00000400
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#define BCM2835_SPI_CS_INTD 0x00000200
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#define BCM2835_SPI_CS_DMAEN 0x00000100
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#define BCM2835_SPI_CS_TA 0x00000080
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#define BCM2835_SPI_CS_CSPOL 0x00000040
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#define BCM2835_SPI_CS_CLEAR_RX 0x00000020
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#define BCM2835_SPI_CS_CLEAR_TX 0x00000010
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#define BCM2835_SPI_CS_CPOL 0x00000008
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#define BCM2835_SPI_CS_CPHA 0x00000004
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#define BCM2835_SPI_CS_CS_10 0x00000002
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#define BCM2835_SPI_CS_CS_01 0x00000001
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#define BCM2835_SPI_TIMEOUT_MS 30000
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#define BCM2835_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_NO_CS)
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#define DRV_NAME "spi-bcm2835"
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struct bcm2835_spi {
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void __iomem *regs;
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struct clk *clk;
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int irq;
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struct completion done;
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const u8 *tx_buf;
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u8 *rx_buf;
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int len;
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};
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static inline u32 bcm2835_rd(struct bcm2835_spi *bs, unsigned reg)
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{
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return readl(bs->regs + reg);
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}
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static inline void bcm2835_wr(struct bcm2835_spi *bs, unsigned reg, u32 val)
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{
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writel(val, bs->regs + reg);
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}
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static inline void bcm2835_rd_fifo(struct bcm2835_spi *bs, int len)
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{
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u8 byte;
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while (len--) {
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byte = bcm2835_rd(bs, BCM2835_SPI_FIFO);
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if (bs->rx_buf)
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*bs->rx_buf++ = byte;
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}
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}
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static inline void bcm2835_wr_fifo(struct bcm2835_spi *bs, int len)
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{
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u8 byte;
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if (len > bs->len)
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len = bs->len;
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while (len--) {
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byte = bs->tx_buf ? *bs->tx_buf++ : 0;
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bcm2835_wr(bs, BCM2835_SPI_FIFO, byte);
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bs->len--;
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}
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}
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static irqreturn_t bcm2835_spi_interrupt(int irq, void *dev_id)
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{
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struct spi_master *master = dev_id;
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struct bcm2835_spi *bs = spi_master_get_devdata(master);
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u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
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/*
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* RXR - RX needs Reading. This means 12 (or more) bytes have been
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* transmitted and hence 12 (or more) bytes have been received.
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*
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* The FIFO is 16-bytes deep. We check for this interrupt to keep the
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* FIFO full; we have a 4-byte-time buffer for IRQ latency. We check
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* this before DONE (TX empty) just in case we delayed processing this
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* interrupt for some reason.
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*
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* We only check for this case if we have more bytes to TX; at the end
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* of the transfer, we ignore this pipelining optimization, and let
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* bcm2835_spi_finish_transfer() drain the RX FIFO.
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*/
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if (bs->len && (cs & BCM2835_SPI_CS_RXR)) {
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/* Read 12 bytes of data */
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bcm2835_rd_fifo(bs, 12);
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/* Write up to 12 bytes */
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bcm2835_wr_fifo(bs, 12);
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/*
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* We must have written something to the TX FIFO due to the
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* bs->len check above, so cannot be DONE. Hence, return
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* early. Note that DONE could also be set if we serviced an
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* RXR interrupt really late.
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*/
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return IRQ_HANDLED;
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}
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/*
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* DONE - TX empty. This occurs when we first enable the transfer
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* since we do not pre-fill the TX FIFO. At any other time, given that
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* we refill the TX FIFO above based on RXR, and hence ignore DONE if
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* RXR is set, DONE really does mean end-of-transfer.
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*/
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if (cs & BCM2835_SPI_CS_DONE) {
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if (bs->len) { /* First interrupt in a transfer */
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bcm2835_wr_fifo(bs, 16);
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} else { /* Transfer complete */
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/* Disable SPI interrupts */
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cs &= ~(BCM2835_SPI_CS_INTR | BCM2835_SPI_CS_INTD);
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bcm2835_wr(bs, BCM2835_SPI_CS, cs);
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/*
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* Wake up bcm2835_spi_transfer_one(), which will call
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* bcm2835_spi_finish_transfer(), to drain the RX FIFO.
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*/
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complete(&bs->done);
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}
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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static int bcm2835_spi_start_transfer(struct spi_device *spi,
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struct spi_transfer *tfr)
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{
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struct bcm2835_spi *bs = spi_master_get_devdata(spi->master);
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unsigned long spi_hz, clk_hz, cdiv;
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u32 cs = BCM2835_SPI_CS_INTR | BCM2835_SPI_CS_INTD | BCM2835_SPI_CS_TA;
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spi_hz = tfr->speed_hz;
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clk_hz = clk_get_rate(bs->clk);
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if (spi_hz >= clk_hz / 2) {
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cdiv = 2; /* clk_hz/2 is the fastest we can go */
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} else if (spi_hz) {
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/* CDIV must be a power of two */
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cdiv = roundup_pow_of_two(DIV_ROUND_UP(clk_hz, spi_hz));
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if (cdiv >= 65536)
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cdiv = 0; /* 0 is the slowest we can go */
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} else
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cdiv = 0; /* 0 is the slowest we can go */
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if (spi->mode & SPI_CPOL)
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cs |= BCM2835_SPI_CS_CPOL;
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if (spi->mode & SPI_CPHA)
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cs |= BCM2835_SPI_CS_CPHA;
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if (!(spi->mode & SPI_NO_CS)) {
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if (spi->mode & SPI_CS_HIGH) {
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cs |= BCM2835_SPI_CS_CSPOL;
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cs |= BCM2835_SPI_CS_CSPOL0 << spi->chip_select;
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}
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cs |= spi->chip_select;
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}
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reinit_completion(&bs->done);
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bs->tx_buf = tfr->tx_buf;
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bs->rx_buf = tfr->rx_buf;
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bs->len = tfr->len;
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bcm2835_wr(bs, BCM2835_SPI_CLK, cdiv);
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/*
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* Enable the HW block. This will immediately trigger a DONE (TX
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* empty) interrupt, upon which we will fill the TX FIFO with the
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* first TX bytes. Pre-filling the TX FIFO here to avoid the
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* interrupt doesn't work:-(
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*/
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bcm2835_wr(bs, BCM2835_SPI_CS, cs);
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return 0;
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}
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static int bcm2835_spi_finish_transfer(struct spi_device *spi,
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struct spi_transfer *tfr, bool cs_change)
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{
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struct bcm2835_spi *bs = spi_master_get_devdata(spi->master);
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u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
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/* Drain RX FIFO */
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while (cs & BCM2835_SPI_CS_RXD) {
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bcm2835_rd_fifo(bs, 1);
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cs = bcm2835_rd(bs, BCM2835_SPI_CS);
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}
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if (tfr->delay_usecs)
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udelay(tfr->delay_usecs);
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if (cs_change)
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/* Clear TA flag */
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bcm2835_wr(bs, BCM2835_SPI_CS, cs & ~BCM2835_SPI_CS_TA);
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return 0;
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}
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static int bcm2835_spi_transfer_one(struct spi_master *master,
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struct spi_message *mesg)
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{
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struct bcm2835_spi *bs = spi_master_get_devdata(master);
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struct spi_transfer *tfr;
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struct spi_device *spi = mesg->spi;
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int err = 0;
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unsigned int timeout;
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bool cs_change;
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list_for_each_entry(tfr, &mesg->transfers, transfer_list) {
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err = bcm2835_spi_start_transfer(spi, tfr);
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if (err)
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goto out;
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timeout = wait_for_completion_timeout(&bs->done,
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msecs_to_jiffies(BCM2835_SPI_TIMEOUT_MS));
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if (!timeout) {
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err = -ETIMEDOUT;
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goto out;
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}
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cs_change = tfr->cs_change ||
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list_is_last(&tfr->transfer_list, &mesg->transfers);
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err = bcm2835_spi_finish_transfer(spi, tfr, cs_change);
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if (err)
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goto out;
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mesg->actual_length += (tfr->len - bs->len);
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}
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out:
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/* Clear FIFOs, and disable the HW block */
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bcm2835_wr(bs, BCM2835_SPI_CS,
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BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);
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mesg->status = err;
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spi_finalize_current_message(master);
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return 0;
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}
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static int bcm2835_spi_probe(struct platform_device *pdev)
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{
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struct spi_master *master;
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struct bcm2835_spi *bs;
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struct resource *res;
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int err;
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master = spi_alloc_master(&pdev->dev, sizeof(*bs));
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if (!master) {
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dev_err(&pdev->dev, "spi_alloc_master() failed\n");
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return -ENOMEM;
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}
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platform_set_drvdata(pdev, master);
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master->mode_bits = BCM2835_SPI_MODE_BITS;
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master->bits_per_word_mask = SPI_BPW_MASK(8);
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master->num_chipselect = 3;
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master->transfer_one_message = bcm2835_spi_transfer_one;
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master->dev.of_node = pdev->dev.of_node;
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bs = spi_master_get_devdata(master);
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init_completion(&bs->done);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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bs->regs = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(bs->regs)) {
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err = PTR_ERR(bs->regs);
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goto out_master_put;
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}
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bs->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(bs->clk)) {
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err = PTR_ERR(bs->clk);
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dev_err(&pdev->dev, "could not get clk: %d\n", err);
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goto out_master_put;
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}
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bs->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
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if (bs->irq <= 0) {
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dev_err(&pdev->dev, "could not get IRQ: %d\n", bs->irq);
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err = bs->irq ? bs->irq : -ENODEV;
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goto out_master_put;
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}
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clk_prepare_enable(bs->clk);
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err = devm_request_irq(&pdev->dev, bs->irq, bcm2835_spi_interrupt, 0,
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dev_name(&pdev->dev), master);
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if (err) {
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dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
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goto out_clk_disable;
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}
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/* initialise the hardware */
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bcm2835_wr(bs, BCM2835_SPI_CS,
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BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);
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err = devm_spi_register_master(&pdev->dev, master);
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if (err) {
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dev_err(&pdev->dev, "could not register SPI master: %d\n", err);
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goto out_clk_disable;
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}
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return 0;
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out_clk_disable:
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clk_disable_unprepare(bs->clk);
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out_master_put:
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spi_master_put(master);
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return err;
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}
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static int bcm2835_spi_remove(struct platform_device *pdev)
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{
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struct spi_master *master = platform_get_drvdata(pdev);
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struct bcm2835_spi *bs = spi_master_get_devdata(master);
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/* Clear FIFOs, and disable the HW block */
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bcm2835_wr(bs, BCM2835_SPI_CS,
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BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);
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clk_disable_unprepare(bs->clk);
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return 0;
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}
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static const struct of_device_id bcm2835_spi_match[] = {
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{ .compatible = "brcm,bcm2835-spi", },
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{}
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};
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MODULE_DEVICE_TABLE(of, bcm2835_spi_match);
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static struct platform_driver bcm2835_spi_driver = {
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.driver = {
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.name = DRV_NAME,
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.of_match_table = bcm2835_spi_match,
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},
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.probe = bcm2835_spi_probe,
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.remove = bcm2835_spi_remove,
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};
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module_platform_driver(bcm2835_spi_driver);
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MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835");
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MODULE_AUTHOR("Chris Boot <bootc@bootc.net>");
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MODULE_LICENSE("GPL v2");
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