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65c662ab63
A platform_driver does not need to set an owner, it will be populated by the driver core. Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
692 lines
18 KiB
C
692 lines
18 KiB
C
/*
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* copyright (c) 2013 Freescale Semiconductor, Inc.
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* Freescale IMX AHCI SATA platform driver
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*
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* based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/ahci_platform.h>
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#include <linux/of_device.h>
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#include <linux/mfd/syscon.h>
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#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
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#include <linux/libata.h>
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#include "ahci.h"
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enum {
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/* Timer 1-ms Register */
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IMX_TIMER1MS = 0x00e0,
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/* Port0 PHY Control Register */
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IMX_P0PHYCR = 0x0178,
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IMX_P0PHYCR_TEST_PDDQ = 1 << 20,
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IMX_P0PHYCR_CR_READ = 1 << 19,
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IMX_P0PHYCR_CR_WRITE = 1 << 18,
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IMX_P0PHYCR_CR_CAP_DATA = 1 << 17,
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IMX_P0PHYCR_CR_CAP_ADDR = 1 << 16,
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/* Port0 PHY Status Register */
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IMX_P0PHYSR = 0x017c,
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IMX_P0PHYSR_CR_ACK = 1 << 18,
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IMX_P0PHYSR_CR_DATA_OUT = 0xffff << 0,
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/* Lane0 Output Status Register */
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IMX_LANE0_OUT_STAT = 0x2003,
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IMX_LANE0_OUT_STAT_RX_PLL_STATE = 1 << 1,
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/* Clock Reset Register */
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IMX_CLOCK_RESET = 0x7f3f,
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IMX_CLOCK_RESET_RESET = 1 << 0,
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};
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enum ahci_imx_type {
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AHCI_IMX53,
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AHCI_IMX6Q,
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};
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struct imx_ahci_priv {
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struct platform_device *ahci_pdev;
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enum ahci_imx_type type;
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struct clk *sata_clk;
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struct clk *sata_ref_clk;
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struct clk *ahb_clk;
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struct regmap *gpr;
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bool no_device;
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bool first_time;
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u32 phy_params;
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};
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static int ahci_imx_hotplug;
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module_param_named(hotplug, ahci_imx_hotplug, int, 0644);
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MODULE_PARM_DESC(hotplug, "AHCI IMX hot-plug support (0=Don't support, 1=support)");
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static void ahci_imx_host_stop(struct ata_host *host);
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static int imx_phy_crbit_assert(void __iomem *mmio, u32 bit, bool assert)
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{
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int timeout = 10;
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u32 crval;
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u32 srval;
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/* Assert or deassert the bit */
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crval = readl(mmio + IMX_P0PHYCR);
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if (assert)
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crval |= bit;
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else
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crval &= ~bit;
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writel(crval, mmio + IMX_P0PHYCR);
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/* Wait for the cr_ack signal */
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do {
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srval = readl(mmio + IMX_P0PHYSR);
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if ((assert ? srval : ~srval) & IMX_P0PHYSR_CR_ACK)
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break;
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usleep_range(100, 200);
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} while (--timeout);
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return timeout ? 0 : -ETIMEDOUT;
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}
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static int imx_phy_reg_addressing(u16 addr, void __iomem *mmio)
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{
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u32 crval = addr;
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int ret;
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/* Supply the address on cr_data_in */
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writel(crval, mmio + IMX_P0PHYCR);
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/* Assert the cr_cap_addr signal */
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ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, true);
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if (ret)
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return ret;
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/* Deassert cr_cap_addr */
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ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, false);
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if (ret)
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return ret;
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return 0;
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}
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static int imx_phy_reg_write(u16 val, void __iomem *mmio)
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{
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u32 crval = val;
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int ret;
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/* Supply the data on cr_data_in */
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writel(crval, mmio + IMX_P0PHYCR);
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/* Assert the cr_cap_data signal */
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ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, true);
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if (ret)
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return ret;
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/* Deassert cr_cap_data */
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ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, false);
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if (ret)
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return ret;
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if (val & IMX_CLOCK_RESET_RESET) {
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/*
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* In case we're resetting the phy, it's unable to acknowledge,
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* so we return immediately here.
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*/
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crval |= IMX_P0PHYCR_CR_WRITE;
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writel(crval, mmio + IMX_P0PHYCR);
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goto out;
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}
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/* Assert the cr_write signal */
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ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, true);
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if (ret)
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return ret;
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/* Deassert cr_write */
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ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, false);
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if (ret)
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return ret;
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out:
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return 0;
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}
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static int imx_phy_reg_read(u16 *val, void __iomem *mmio)
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{
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int ret;
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/* Assert the cr_read signal */
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ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, true);
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if (ret)
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return ret;
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/* Capture the data from cr_data_out[] */
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*val = readl(mmio + IMX_P0PHYSR) & IMX_P0PHYSR_CR_DATA_OUT;
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/* Deassert cr_read */
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ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, false);
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if (ret)
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return ret;
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return 0;
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}
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static int imx_sata_phy_reset(struct ahci_host_priv *hpriv)
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{
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void __iomem *mmio = hpriv->mmio;
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int timeout = 10;
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u16 val;
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int ret;
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/* Reset SATA PHY by setting RESET bit of PHY register CLOCK_RESET */
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ret = imx_phy_reg_addressing(IMX_CLOCK_RESET, mmio);
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if (ret)
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return ret;
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ret = imx_phy_reg_write(IMX_CLOCK_RESET_RESET, mmio);
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if (ret)
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return ret;
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/* Wait for PHY RX_PLL to be stable */
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do {
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usleep_range(100, 200);
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ret = imx_phy_reg_addressing(IMX_LANE0_OUT_STAT, mmio);
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if (ret)
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return ret;
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ret = imx_phy_reg_read(&val, mmio);
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if (ret)
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return ret;
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if (val & IMX_LANE0_OUT_STAT_RX_PLL_STATE)
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break;
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} while (--timeout);
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return timeout ? 0 : -ETIMEDOUT;
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}
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static int imx_sata_enable(struct ahci_host_priv *hpriv)
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{
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struct imx_ahci_priv *imxpriv = hpriv->plat_data;
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struct device *dev = &imxpriv->ahci_pdev->dev;
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int ret;
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if (imxpriv->no_device)
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return 0;
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if (hpriv->target_pwr) {
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ret = regulator_enable(hpriv->target_pwr);
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if (ret)
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return ret;
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}
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ret = clk_prepare_enable(imxpriv->sata_ref_clk);
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if (ret < 0)
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goto disable_regulator;
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if (imxpriv->type == AHCI_IMX6Q) {
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/*
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* set PHY Paremeters, two steps to configure the GPR13,
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* one write for rest of parameters, mask of first write
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* is 0x07ffffff, and the other one write for setting
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* the mpll_clk_en.
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*/
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regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
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IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK |
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IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK |
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IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK |
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IMX6Q_GPR13_SATA_SPD_MODE_MASK |
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IMX6Q_GPR13_SATA_MPLL_SS_EN |
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IMX6Q_GPR13_SATA_TX_ATTEN_MASK |
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IMX6Q_GPR13_SATA_TX_BOOST_MASK |
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IMX6Q_GPR13_SATA_TX_LVL_MASK |
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IMX6Q_GPR13_SATA_MPLL_CLK_EN |
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IMX6Q_GPR13_SATA_TX_EDGE_RATE,
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imxpriv->phy_params);
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regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
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IMX6Q_GPR13_SATA_MPLL_CLK_EN,
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IMX6Q_GPR13_SATA_MPLL_CLK_EN);
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usleep_range(100, 200);
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ret = imx_sata_phy_reset(hpriv);
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if (ret) {
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dev_err(dev, "failed to reset phy: %d\n", ret);
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goto disable_clk;
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}
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}
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usleep_range(1000, 2000);
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return 0;
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disable_clk:
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clk_disable_unprepare(imxpriv->sata_ref_clk);
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disable_regulator:
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if (hpriv->target_pwr)
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regulator_disable(hpriv->target_pwr);
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return ret;
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}
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static void imx_sata_disable(struct ahci_host_priv *hpriv)
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{
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struct imx_ahci_priv *imxpriv = hpriv->plat_data;
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if (imxpriv->no_device)
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return;
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if (imxpriv->type == AHCI_IMX6Q) {
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regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
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IMX6Q_GPR13_SATA_MPLL_CLK_EN,
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!IMX6Q_GPR13_SATA_MPLL_CLK_EN);
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}
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clk_disable_unprepare(imxpriv->sata_ref_clk);
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if (hpriv->target_pwr)
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regulator_disable(hpriv->target_pwr);
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}
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static void ahci_imx_error_handler(struct ata_port *ap)
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{
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u32 reg_val;
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struct ata_device *dev;
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struct ata_host *host = dev_get_drvdata(ap->dev);
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struct ahci_host_priv *hpriv = host->private_data;
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void __iomem *mmio = hpriv->mmio;
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struct imx_ahci_priv *imxpriv = hpriv->plat_data;
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ahci_error_handler(ap);
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if (!(imxpriv->first_time) || ahci_imx_hotplug)
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return;
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imxpriv->first_time = false;
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ata_for_each_dev(dev, &ap->link, ENABLED)
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return;
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/*
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* Disable link to save power. An imx ahci port can't be recovered
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* without full reset once the pddq mode is enabled making it
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* impossible to use as part of libata LPM.
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*/
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reg_val = readl(mmio + IMX_P0PHYCR);
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writel(reg_val | IMX_P0PHYCR_TEST_PDDQ, mmio + IMX_P0PHYCR);
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imx_sata_disable(hpriv);
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imxpriv->no_device = true;
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dev_info(ap->dev, "no device found, disabling link.\n");
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dev_info(ap->dev, "pass " MODULE_PARAM_PREFIX ".hotplug=1 to enable hotplug\n");
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}
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static int ahci_imx_softreset(struct ata_link *link, unsigned int *class,
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unsigned long deadline)
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{
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struct ata_port *ap = link->ap;
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struct ata_host *host = dev_get_drvdata(ap->dev);
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struct ahci_host_priv *hpriv = host->private_data;
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struct imx_ahci_priv *imxpriv = hpriv->plat_data;
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int ret = -EIO;
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if (imxpriv->type == AHCI_IMX53)
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ret = ahci_pmp_retry_srst_ops.softreset(link, class, deadline);
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else if (imxpriv->type == AHCI_IMX6Q)
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ret = ahci_ops.softreset(link, class, deadline);
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return ret;
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}
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static struct ata_port_operations ahci_imx_ops = {
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.inherits = &ahci_ops,
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.host_stop = ahci_imx_host_stop,
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.error_handler = ahci_imx_error_handler,
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.softreset = ahci_imx_softreset,
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};
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static const struct ata_port_info ahci_imx_port_info = {
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.flags = AHCI_FLAG_COMMON,
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.pio_mask = ATA_PIO4,
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.udma_mask = ATA_UDMA6,
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.port_ops = &ahci_imx_ops,
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};
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static const struct of_device_id imx_ahci_of_match[] = {
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{ .compatible = "fsl,imx53-ahci", .data = (void *)AHCI_IMX53 },
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{ .compatible = "fsl,imx6q-ahci", .data = (void *)AHCI_IMX6Q },
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{},
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};
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MODULE_DEVICE_TABLE(of, imx_ahci_of_match);
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struct reg_value {
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u32 of_value;
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u32 reg_value;
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};
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struct reg_property {
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const char *name;
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const struct reg_value *values;
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size_t num_values;
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u32 def_value;
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u32 set_value;
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};
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static const struct reg_value gpr13_tx_level[] = {
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{ 937, IMX6Q_GPR13_SATA_TX_LVL_0_937_V },
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{ 947, IMX6Q_GPR13_SATA_TX_LVL_0_947_V },
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{ 957, IMX6Q_GPR13_SATA_TX_LVL_0_957_V },
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{ 966, IMX6Q_GPR13_SATA_TX_LVL_0_966_V },
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{ 976, IMX6Q_GPR13_SATA_TX_LVL_0_976_V },
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{ 986, IMX6Q_GPR13_SATA_TX_LVL_0_986_V },
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{ 996, IMX6Q_GPR13_SATA_TX_LVL_0_996_V },
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{ 1005, IMX6Q_GPR13_SATA_TX_LVL_1_005_V },
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{ 1015, IMX6Q_GPR13_SATA_TX_LVL_1_015_V },
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{ 1025, IMX6Q_GPR13_SATA_TX_LVL_1_025_V },
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{ 1035, IMX6Q_GPR13_SATA_TX_LVL_1_035_V },
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{ 1045, IMX6Q_GPR13_SATA_TX_LVL_1_045_V },
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{ 1054, IMX6Q_GPR13_SATA_TX_LVL_1_054_V },
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{ 1064, IMX6Q_GPR13_SATA_TX_LVL_1_064_V },
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{ 1074, IMX6Q_GPR13_SATA_TX_LVL_1_074_V },
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{ 1084, IMX6Q_GPR13_SATA_TX_LVL_1_084_V },
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{ 1094, IMX6Q_GPR13_SATA_TX_LVL_1_094_V },
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{ 1104, IMX6Q_GPR13_SATA_TX_LVL_1_104_V },
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{ 1113, IMX6Q_GPR13_SATA_TX_LVL_1_113_V },
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{ 1123, IMX6Q_GPR13_SATA_TX_LVL_1_123_V },
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{ 1133, IMX6Q_GPR13_SATA_TX_LVL_1_133_V },
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{ 1143, IMX6Q_GPR13_SATA_TX_LVL_1_143_V },
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{ 1152, IMX6Q_GPR13_SATA_TX_LVL_1_152_V },
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{ 1162, IMX6Q_GPR13_SATA_TX_LVL_1_162_V },
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{ 1172, IMX6Q_GPR13_SATA_TX_LVL_1_172_V },
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{ 1182, IMX6Q_GPR13_SATA_TX_LVL_1_182_V },
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{ 1191, IMX6Q_GPR13_SATA_TX_LVL_1_191_V },
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{ 1201, IMX6Q_GPR13_SATA_TX_LVL_1_201_V },
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{ 1211, IMX6Q_GPR13_SATA_TX_LVL_1_211_V },
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{ 1221, IMX6Q_GPR13_SATA_TX_LVL_1_221_V },
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{ 1230, IMX6Q_GPR13_SATA_TX_LVL_1_230_V },
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{ 1240, IMX6Q_GPR13_SATA_TX_LVL_1_240_V }
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};
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static const struct reg_value gpr13_tx_boost[] = {
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{ 0, IMX6Q_GPR13_SATA_TX_BOOST_0_00_DB },
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{ 370, IMX6Q_GPR13_SATA_TX_BOOST_0_37_DB },
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{ 740, IMX6Q_GPR13_SATA_TX_BOOST_0_74_DB },
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{ 1110, IMX6Q_GPR13_SATA_TX_BOOST_1_11_DB },
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{ 1480, IMX6Q_GPR13_SATA_TX_BOOST_1_48_DB },
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{ 1850, IMX6Q_GPR13_SATA_TX_BOOST_1_85_DB },
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{ 2220, IMX6Q_GPR13_SATA_TX_BOOST_2_22_DB },
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{ 2590, IMX6Q_GPR13_SATA_TX_BOOST_2_59_DB },
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{ 2960, IMX6Q_GPR13_SATA_TX_BOOST_2_96_DB },
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{ 3330, IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB },
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{ 3700, IMX6Q_GPR13_SATA_TX_BOOST_3_70_DB },
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{ 4070, IMX6Q_GPR13_SATA_TX_BOOST_4_07_DB },
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{ 4440, IMX6Q_GPR13_SATA_TX_BOOST_4_44_DB },
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{ 4810, IMX6Q_GPR13_SATA_TX_BOOST_4_81_DB },
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{ 5280, IMX6Q_GPR13_SATA_TX_BOOST_5_28_DB },
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{ 5750, IMX6Q_GPR13_SATA_TX_BOOST_5_75_DB }
|
|
};
|
|
|
|
static const struct reg_value gpr13_tx_atten[] = {
|
|
{ 8, IMX6Q_GPR13_SATA_TX_ATTEN_8_16 },
|
|
{ 9, IMX6Q_GPR13_SATA_TX_ATTEN_9_16 },
|
|
{ 10, IMX6Q_GPR13_SATA_TX_ATTEN_10_16 },
|
|
{ 12, IMX6Q_GPR13_SATA_TX_ATTEN_12_16 },
|
|
{ 14, IMX6Q_GPR13_SATA_TX_ATTEN_14_16 },
|
|
{ 16, IMX6Q_GPR13_SATA_TX_ATTEN_16_16 },
|
|
};
|
|
|
|
static const struct reg_value gpr13_rx_eq[] = {
|
|
{ 500, IMX6Q_GPR13_SATA_RX_EQ_VAL_0_5_DB },
|
|
{ 1000, IMX6Q_GPR13_SATA_RX_EQ_VAL_1_0_DB },
|
|
{ 1500, IMX6Q_GPR13_SATA_RX_EQ_VAL_1_5_DB },
|
|
{ 2000, IMX6Q_GPR13_SATA_RX_EQ_VAL_2_0_DB },
|
|
{ 2500, IMX6Q_GPR13_SATA_RX_EQ_VAL_2_5_DB },
|
|
{ 3000, IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB },
|
|
{ 3500, IMX6Q_GPR13_SATA_RX_EQ_VAL_3_5_DB },
|
|
{ 4000, IMX6Q_GPR13_SATA_RX_EQ_VAL_4_0_DB },
|
|
};
|
|
|
|
static const struct reg_property gpr13_props[] = {
|
|
{
|
|
.name = "fsl,transmit-level-mV",
|
|
.values = gpr13_tx_level,
|
|
.num_values = ARRAY_SIZE(gpr13_tx_level),
|
|
.def_value = IMX6Q_GPR13_SATA_TX_LVL_1_025_V,
|
|
}, {
|
|
.name = "fsl,transmit-boost-mdB",
|
|
.values = gpr13_tx_boost,
|
|
.num_values = ARRAY_SIZE(gpr13_tx_boost),
|
|
.def_value = IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB,
|
|
}, {
|
|
.name = "fsl,transmit-atten-16ths",
|
|
.values = gpr13_tx_atten,
|
|
.num_values = ARRAY_SIZE(gpr13_tx_atten),
|
|
.def_value = IMX6Q_GPR13_SATA_TX_ATTEN_9_16,
|
|
}, {
|
|
.name = "fsl,receive-eq-mdB",
|
|
.values = gpr13_rx_eq,
|
|
.num_values = ARRAY_SIZE(gpr13_rx_eq),
|
|
.def_value = IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB,
|
|
}, {
|
|
.name = "fsl,no-spread-spectrum",
|
|
.def_value = IMX6Q_GPR13_SATA_MPLL_SS_EN,
|
|
.set_value = 0,
|
|
},
|
|
};
|
|
|
|
static u32 imx_ahci_parse_props(struct device *dev,
|
|
const struct reg_property *prop, size_t num)
|
|
{
|
|
struct device_node *np = dev->of_node;
|
|
u32 reg_value = 0;
|
|
int i, j;
|
|
|
|
for (i = 0; i < num; i++, prop++) {
|
|
u32 of_val;
|
|
|
|
if (prop->num_values == 0) {
|
|
if (of_property_read_bool(np, prop->name))
|
|
reg_value |= prop->set_value;
|
|
else
|
|
reg_value |= prop->def_value;
|
|
continue;
|
|
}
|
|
|
|
if (of_property_read_u32(np, prop->name, &of_val)) {
|
|
dev_info(dev, "%s not specified, using %08x\n",
|
|
prop->name, prop->def_value);
|
|
reg_value |= prop->def_value;
|
|
continue;
|
|
}
|
|
|
|
for (j = 0; j < prop->num_values; j++) {
|
|
if (prop->values[j].of_value == of_val) {
|
|
dev_info(dev, "%s value %u, using %08x\n",
|
|
prop->name, of_val, prop->values[j].reg_value);
|
|
reg_value |= prop->values[j].reg_value;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (j == prop->num_values) {
|
|
dev_err(dev, "DT property %s is not a valid value\n",
|
|
prop->name);
|
|
reg_value |= prop->def_value;
|
|
}
|
|
}
|
|
|
|
return reg_value;
|
|
}
|
|
|
|
static int imx_ahci_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
const struct of_device_id *of_id;
|
|
struct ahci_host_priv *hpriv;
|
|
struct imx_ahci_priv *imxpriv;
|
|
unsigned int reg_val;
|
|
int ret;
|
|
|
|
of_id = of_match_device(imx_ahci_of_match, dev);
|
|
if (!of_id)
|
|
return -EINVAL;
|
|
|
|
imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL);
|
|
if (!imxpriv)
|
|
return -ENOMEM;
|
|
|
|
imxpriv->ahci_pdev = pdev;
|
|
imxpriv->no_device = false;
|
|
imxpriv->first_time = true;
|
|
imxpriv->type = (enum ahci_imx_type)of_id->data;
|
|
|
|
imxpriv->sata_clk = devm_clk_get(dev, "sata");
|
|
if (IS_ERR(imxpriv->sata_clk)) {
|
|
dev_err(dev, "can't get sata clock.\n");
|
|
return PTR_ERR(imxpriv->sata_clk);
|
|
}
|
|
|
|
imxpriv->sata_ref_clk = devm_clk_get(dev, "sata_ref");
|
|
if (IS_ERR(imxpriv->sata_ref_clk)) {
|
|
dev_err(dev, "can't get sata_ref clock.\n");
|
|
return PTR_ERR(imxpriv->sata_ref_clk);
|
|
}
|
|
|
|
imxpriv->ahb_clk = devm_clk_get(dev, "ahb");
|
|
if (IS_ERR(imxpriv->ahb_clk)) {
|
|
dev_err(dev, "can't get ahb clock.\n");
|
|
return PTR_ERR(imxpriv->ahb_clk);
|
|
}
|
|
|
|
if (imxpriv->type == AHCI_IMX6Q) {
|
|
u32 reg_value;
|
|
|
|
imxpriv->gpr = syscon_regmap_lookup_by_compatible(
|
|
"fsl,imx6q-iomuxc-gpr");
|
|
if (IS_ERR(imxpriv->gpr)) {
|
|
dev_err(dev,
|
|
"failed to find fsl,imx6q-iomux-gpr regmap\n");
|
|
return PTR_ERR(imxpriv->gpr);
|
|
}
|
|
|
|
reg_value = imx_ahci_parse_props(dev, gpr13_props,
|
|
ARRAY_SIZE(gpr13_props));
|
|
|
|
imxpriv->phy_params =
|
|
IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M |
|
|
IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F |
|
|
IMX6Q_GPR13_SATA_SPD_MODE_3P0G |
|
|
reg_value;
|
|
}
|
|
|
|
hpriv = ahci_platform_get_resources(pdev);
|
|
if (IS_ERR(hpriv))
|
|
return PTR_ERR(hpriv);
|
|
|
|
hpriv->plat_data = imxpriv;
|
|
|
|
ret = clk_prepare_enable(imxpriv->sata_clk);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = imx_sata_enable(hpriv);
|
|
if (ret)
|
|
goto disable_clk;
|
|
|
|
/*
|
|
* Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
|
|
* and IP vendor specific register IMX_TIMER1MS.
|
|
* Configure CAP_SSS (support stagered spin up).
|
|
* Implement the port0.
|
|
* Get the ahb clock rate, and configure the TIMER1MS register.
|
|
*/
|
|
reg_val = readl(hpriv->mmio + HOST_CAP);
|
|
if (!(reg_val & HOST_CAP_SSS)) {
|
|
reg_val |= HOST_CAP_SSS;
|
|
writel(reg_val, hpriv->mmio + HOST_CAP);
|
|
}
|
|
reg_val = readl(hpriv->mmio + HOST_PORTS_IMPL);
|
|
if (!(reg_val & 0x1)) {
|
|
reg_val |= 0x1;
|
|
writel(reg_val, hpriv->mmio + HOST_PORTS_IMPL);
|
|
}
|
|
|
|
reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;
|
|
writel(reg_val, hpriv->mmio + IMX_TIMER1MS);
|
|
|
|
ret = ahci_platform_init_host(pdev, hpriv, &ahci_imx_port_info);
|
|
if (ret)
|
|
goto disable_sata;
|
|
|
|
return 0;
|
|
|
|
disable_sata:
|
|
imx_sata_disable(hpriv);
|
|
disable_clk:
|
|
clk_disable_unprepare(imxpriv->sata_clk);
|
|
return ret;
|
|
}
|
|
|
|
static void ahci_imx_host_stop(struct ata_host *host)
|
|
{
|
|
struct ahci_host_priv *hpriv = host->private_data;
|
|
struct imx_ahci_priv *imxpriv = hpriv->plat_data;
|
|
|
|
imx_sata_disable(hpriv);
|
|
clk_disable_unprepare(imxpriv->sata_clk);
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int imx_ahci_suspend(struct device *dev)
|
|
{
|
|
struct ata_host *host = dev_get_drvdata(dev);
|
|
struct ahci_host_priv *hpriv = host->private_data;
|
|
int ret;
|
|
|
|
ret = ahci_platform_suspend_host(dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
imx_sata_disable(hpriv);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int imx_ahci_resume(struct device *dev)
|
|
{
|
|
struct ata_host *host = dev_get_drvdata(dev);
|
|
struct ahci_host_priv *hpriv = host->private_data;
|
|
int ret;
|
|
|
|
ret = imx_sata_enable(hpriv);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return ahci_platform_resume_host(dev);
|
|
}
|
|
#endif
|
|
|
|
static SIMPLE_DEV_PM_OPS(ahci_imx_pm_ops, imx_ahci_suspend, imx_ahci_resume);
|
|
|
|
static struct platform_driver imx_ahci_driver = {
|
|
.probe = imx_ahci_probe,
|
|
.remove = ata_platform_remove_one,
|
|
.driver = {
|
|
.name = "ahci-imx",
|
|
.of_match_table = imx_ahci_of_match,
|
|
.pm = &ahci_imx_pm_ops,
|
|
},
|
|
};
|
|
module_platform_driver(imx_ahci_driver);
|
|
|
|
MODULE_DESCRIPTION("Freescale i.MX AHCI SATA platform driver");
|
|
MODULE_AUTHOR("Richard Zhu <Hong-Xing.Zhu@freescale.com>");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS("ahci:imx");
|