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Bindings for Qualcomm Quad SPI used on SoCs such as sdm845. Signed-off-by: Girish Mahadevan <girishm@codeaurora.org> Signed-off-by: Ryan Case <ryandcase@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Mark Brown <broonie@kernel.org>
37 lines
1.2 KiB
Plaintext
37 lines
1.2 KiB
Plaintext
Qualcomm Quad Serial Peripheral Interface (QSPI)
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The QSPI controller allows SPI protocol communication in single, dual, or quad
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wire transmission modes for read/write access to slaves such as NOR flash.
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Required properties:
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- compatible: An SoC specific identifier followed by "qcom,qspi-v1", such as
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"qcom,sdm845-qspi", "qcom,qspi-v1"
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- reg: Should contain the base register location and length.
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- interrupts: Interrupt number used by the controller.
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- clocks: Should contain the core and AHB clock.
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- clock-names: Should be "core" for core clock and "iface" for AHB clock.
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SPI slave nodes must be children of the SPI master node and can contain
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properties described in Documentation/devicetree/bindings/spi/spi-bus.txt
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Example:
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qspi: spi@88df000 {
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compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
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reg = <0x88df000 0x600>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "iface", "core";
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clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
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<&gcc GCC_QSPI_CORE_CLK>;
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <25000000>;
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spi-tx-bus-width = <2>;
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spi-rx-bus-width = <2>;
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};
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};
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