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5b02c51af4
Fix sh7377 and sh73a0 build failure: drivers/tty/serial/sh-sci.c: In function 'scif_txfill': drivers/tty/serial/sh-sci.c:338: error: implicit declaration of function 'sci_SCTFDR_in' drivers/tty/serial/sh-sci.c: In function 'scif_rxfill': drivers/tty/serial/sh-sci.c:351: error: implicit declaration of function 'sci_SCRFDR_in' make[3]: *** [drivers/tty/serial/sh-sci.o] Error 1 make[2]: *** [drivers/tty/serial] Error 2 make[1]: *** [drivers/tty] Error 2 make: *** [drivers] Error 2 Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
469 lines
18 KiB
C
469 lines
18 KiB
C
#include <linux/serial_core.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
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#include <asm/regs306x.h>
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#endif
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#if defined(CONFIG_H8S2678)
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#include <asm/regs267x.h>
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
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defined(CONFIG_CPU_SUBTYPE_SH7707) || \
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defined(CONFIG_CPU_SUBTYPE_SH7708) || \
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defined(CONFIG_CPU_SUBTYPE_SH7709)
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# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
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# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
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#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
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# define SCIF0 0xA4400000
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# define SCIF2 0xA4410000
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# define SCPCR 0xA4000116
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# define SCPDR 0xA4000136
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#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
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defined(CONFIG_CPU_SUBTYPE_SH7721) || \
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defined(CONFIG_ARCH_SH73A0) || \
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defined(CONFIG_ARCH_SH7367) || \
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defined(CONFIG_ARCH_SH7377) || \
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defined(CONFIG_ARCH_SH7372)
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# define PORT_PTCR 0xA405011EUL
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# define PORT_PVCR 0xA4050122UL
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# define SCIF_ORER 0x0200 /* overrun error bit */
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#elif defined(CONFIG_SH_RTS7751R2D)
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# define SCSPTR1 0xFFE0001C /* 8 bit SCIF */
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# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
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# define SCIF_ORER 0x0001 /* overrun error bit */
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#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
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defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
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defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
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defined(CONFIG_CPU_SUBTYPE_SH7091) || \
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defined(CONFIG_CPU_SUBTYPE_SH7751) || \
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defined(CONFIG_CPU_SUBTYPE_SH7751R)
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# define SCSPTR1 0xffe0001c /* 8 bit SCI */
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# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
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# define SCIF_ORER 0x0001 /* overrun error bit */
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#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
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# define SCSPTR0 0xfe600024 /* 16 bit SCIF */
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# define SCSPTR1 0xfe610024 /* 16 bit SCIF */
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# define SCSPTR2 0xfe620024 /* 16 bit SCIF */
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# define SCIF_ORER 0x0001 /* overrun error bit */
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#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
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# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
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# define SCIF_ORER 0x0001 /* overrun error bit */
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# define PACR 0xa4050100
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# define PBCR 0xa4050102
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#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
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# define SCSPTR0 0xffe00010 /* 16 bit SCIF */
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#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
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# define PADR 0xA4050120
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# define PSDR 0xA405013e
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# define PWDR 0xA4050166
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# define PSCR 0xA405011E
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# define SCIF_ORER 0x0001 /* overrun error bit */
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#elif defined(CONFIG_CPU_SUBTYPE_SH7366)
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# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
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# define SCSPTR0 SCPDR0
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# define SCIF_ORER 0x0001 /* overrun error bit */
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#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
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# define SCSPTR0 0xa4050160
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# define SCIF_ORER 0x0001 /* overrun error bit */
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#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
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# define SCIF_ORER 0x0001 /* overrun error bit */
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#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
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# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
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# define SCIF_ORER 0x0001 /* overrun error bit */
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#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
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# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
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#elif defined(CONFIG_H8S2678)
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# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
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#elif defined(CONFIG_CPU_SUBTYPE_SH7757)
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# define SCSPTR0 0xfe4b0020
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# define SCIF_ORER 0x0001
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#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
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# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
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# define SCIF_ORER 0x0001 /* overrun error bit */
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#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
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# define SCSPTR0 0xff923020 /* 16 bit SCIF */
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# define SCIF_ORER 0x0001 /* overrun error bit */
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#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
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# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
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# define SCIF_ORER 0x0001 /* Overrun error bit */
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#elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \
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defined(CONFIG_CPU_SUBTYPE_SH7786)
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# define SCSPTR0 0xffea0024 /* 16 bit SCIF */
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# define SCIF_ORER 0x0001 /* Overrun error bit */
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#elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \
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defined(CONFIG_CPU_SUBTYPE_SH7203) || \
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defined(CONFIG_CPU_SUBTYPE_SH7206) || \
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defined(CONFIG_CPU_SUBTYPE_SH7263)
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# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
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#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
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# define SCSPTR0 0xf8400020 /* 16 bit SCIF */
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# define SCIF_ORER 0x0001 /* overrun error bit */
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#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
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# define SCSPTR0 0xffc30020 /* 16 bit SCIF */
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# define SCIF_ORER 0x0001 /* Overrun error bit */
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#else
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# error CPU subtype not defined
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#endif
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/* SCxSR SCI */
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#define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
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#define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
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#define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
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#define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
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#define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
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#define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
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/* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
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/* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
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#define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
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/* SCxSR SCIF */
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#define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
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#define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
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#define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
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#define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
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#define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
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#define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
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#define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
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#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
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#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
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defined(CONFIG_CPU_SUBTYPE_SH7720) || \
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defined(CONFIG_CPU_SUBTYPE_SH7721) || \
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defined(CONFIG_ARCH_SH73A0) || \
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defined(CONFIG_ARCH_SH7367) || \
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defined(CONFIG_ARCH_SH7377) || \
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defined(CONFIG_ARCH_SH7372)
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# define SCIF_ORER 0x0200
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# define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
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# define SCIF_RFDC_MASK 0x007f
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# define SCIF_TXROOM_MAX 64
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#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
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# define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK )
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# define SCIF_RFDC_MASK 0x007f
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# define SCIF_TXROOM_MAX 64
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/* SH7763 SCIF2 support */
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# define SCIF2_RFDC_MASK 0x001f
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# define SCIF2_TXROOM_MAX 16
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#else
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# define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
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# define SCIF_RFDC_MASK 0x001f
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# define SCIF_TXROOM_MAX 16
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#endif
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#ifndef SCIF_ORER
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#define SCIF_ORER 0x0000
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#endif
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#define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
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#define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
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#define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
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#define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
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#define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
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#define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
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#define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
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#define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER)
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#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
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defined(CONFIG_CPU_SUBTYPE_SH7720) || \
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defined(CONFIG_CPU_SUBTYPE_SH7721) || \
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defined(CONFIG_ARCH_SH73A0) || \
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defined(CONFIG_ARCH_SH7367) || \
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defined(CONFIG_ARCH_SH7377) || \
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defined(CONFIG_ARCH_SH7372)
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# define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc)
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# define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73)
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# define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf)
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# define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3)
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#else
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# define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
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# define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
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# define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
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# define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
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#endif
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/* SCFCR */
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#define SCFCR_RFRST 0x0002
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#define SCFCR_TFRST 0x0004
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#define SCFCR_MCE 0x0008
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#define SCI_MAJOR 204
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#define SCI_MINOR_START 8
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#define SCI_IN(size, offset) \
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if ((size) == 8) { \
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return ioread8(port->membase + (offset)); \
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} else { \
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return ioread16(port->membase + (offset)); \
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}
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#define SCI_OUT(size, offset, value) \
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if ((size) == 8) { \
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iowrite8(value, port->membase + (offset)); \
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} else if ((size) == 16) { \
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iowrite16(value, port->membase + (offset)); \
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}
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#define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
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static inline unsigned int sci_##name##_in(struct uart_port *port) \
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{ \
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if (port->type == PORT_SCIF || port->type == PORT_SCIFB) { \
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SCI_IN(scif_size, scif_offset) \
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} else { /* PORT_SCI or PORT_SCIFA */ \
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SCI_IN(sci_size, sci_offset); \
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} \
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} \
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static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
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{ \
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if (port->type == PORT_SCIF || port->type == PORT_SCIFB) { \
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SCI_OUT(scif_size, scif_offset, value) \
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} else { /* PORT_SCI or PORT_SCIFA */ \
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SCI_OUT(sci_size, sci_offset, value); \
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} \
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}
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#ifdef CONFIG_H8300
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/* h8300 don't have SCIF */
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#define CPU_SCIF_FNS(name) \
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static inline unsigned int sci_##name##_in(struct uart_port *port) \
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{ \
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return 0; \
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} \
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static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
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{ \
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}
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#else
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#define CPU_SCIF_FNS(name, scif_offset, scif_size) \
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static inline unsigned int sci_##name##_in(struct uart_port *port) \
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{ \
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SCI_IN(scif_size, scif_offset); \
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} \
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static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
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{ \
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SCI_OUT(scif_size, scif_offset, value); \
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}
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#endif
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#define CPU_SCI_FNS(name, sci_offset, sci_size) \
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static inline unsigned int sci_##name##_in(struct uart_port* port) \
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{ \
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SCI_IN(sci_size, sci_offset); \
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} \
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static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \
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{ \
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SCI_OUT(sci_size, sci_offset, value); \
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}
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#if defined(CONFIG_CPU_SH3) || \
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defined(CONFIG_ARCH_SH73A0) || \
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defined(CONFIG_ARCH_SH7367) || \
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defined(CONFIG_ARCH_SH7377) || \
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defined(CONFIG_ARCH_SH7372)
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#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
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#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
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sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
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h8_sci_offset, h8_sci_size) \
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CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
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#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
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CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
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#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
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defined(CONFIG_CPU_SUBTYPE_SH7720) || \
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defined(CONFIG_CPU_SUBTYPE_SH7721) || \
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defined(CONFIG_ARCH_SH7367)
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#define SCIF_FNS(name, scif_offset, scif_size) \
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CPU_SCIF_FNS(name, scif_offset, scif_size)
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#elif defined(CONFIG_ARCH_SH7377) || \
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defined(CONFIG_ARCH_SH7372) || \
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defined(CONFIG_ARCH_SH73A0)
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#define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scifb_offset, sh4_scifb_size) \
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CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scifb_offset, sh4_scifb_size)
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#define SCIF_FNS(name, scif_offset, scif_size) \
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CPU_SCIF_FNS(name, scif_offset, scif_size)
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#else
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#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
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sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
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h8_sci_offset, h8_sci_size) \
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CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
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#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
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CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
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#endif
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#elif defined(__H8300H__) || defined(__H8300S__)
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#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
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sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
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h8_sci_offset, h8_sci_size) \
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CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
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#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
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CPU_SCIF_FNS(name)
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#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
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defined(CONFIG_CPU_SUBTYPE_SH7724)
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#define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) \
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CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size)
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#define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
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CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
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#else
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#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
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sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
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h8_sci_offset, h8_sci_size) \
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CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
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#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
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CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
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defined(CONFIG_CPU_SUBTYPE_SH7720) || \
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defined(CONFIG_CPU_SUBTYPE_SH7721) || \
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defined(CONFIG_ARCH_SH7367)
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SCIF_FNS(SCSMR, 0x00, 16)
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SCIF_FNS(SCBRR, 0x04, 8)
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SCIF_FNS(SCSCR, 0x08, 16)
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SCIF_FNS(SCxSR, 0x14, 16)
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SCIF_FNS(SCFCR, 0x18, 16)
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SCIF_FNS(SCFDR, 0x1c, 16)
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SCIF_FNS(SCxTDR, 0x20, 8)
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SCIF_FNS(SCxRDR, 0x24, 8)
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SCIF_FNS(SCLSR, 0x00, 0)
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#elif defined(CONFIG_ARCH_SH7377) || \
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defined(CONFIG_ARCH_SH7372) || \
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defined(CONFIG_ARCH_SH73A0)
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SCIF_FNS(SCSMR, 0x00, 16)
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SCIF_FNS(SCBRR, 0x04, 8)
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SCIF_FNS(SCSCR, 0x08, 16)
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SCIF_FNS(SCTDSR, 0x0c, 16)
|
|
SCIF_FNS(SCFER, 0x10, 16)
|
|
SCIF_FNS(SCxSR, 0x14, 16)
|
|
SCIF_FNS(SCFCR, 0x18, 16)
|
|
SCIF_FNS(SCFDR, 0x1c, 16)
|
|
SCIF_FNS(SCTFDR, 0x38, 16)
|
|
SCIF_FNS(SCRFDR, 0x3c, 16)
|
|
SCIx_FNS(SCxTDR, 0x20, 8, 0x40, 8)
|
|
SCIx_FNS(SCxRDR, 0x24, 8, 0x60, 8)
|
|
SCIF_FNS(SCLSR, 0x00, 0)
|
|
#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
|
|
defined(CONFIG_CPU_SUBTYPE_SH7724)
|
|
SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16)
|
|
SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8)
|
|
SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16)
|
|
SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8)
|
|
SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16)
|
|
SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8)
|
|
SCIx_FNS(SCSPTR, 0, 0, 0, 0)
|
|
SCIF_FNS(SCFCR, 0x18, 16)
|
|
SCIF_FNS(SCFDR, 0x1c, 16)
|
|
SCIF_FNS(SCLSR, 0x24, 16)
|
|
#else
|
|
/* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
|
|
/* name off sz off sz off sz off sz off sz*/
|
|
SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8)
|
|
SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8)
|
|
SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8)
|
|
SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
|
|
SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
|
|
SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
|
|
SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
|
|
#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
|
|
defined(CONFIG_CPU_SUBTYPE_SH7780) || \
|
|
defined(CONFIG_CPU_SUBTYPE_SH7785) || \
|
|
defined(CONFIG_CPU_SUBTYPE_SH7786)
|
|
SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
|
|
SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
|
|
SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
|
|
SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
|
|
SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
|
|
#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
|
|
SCIF_FNS(SCFDR, 0, 0, 0x1C, 16)
|
|
SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
|
|
SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
|
|
SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
|
|
SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
|
|
#else
|
|
SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
|
|
#if defined(CONFIG_CPU_SUBTYPE_SH7722)
|
|
SCIF_FNS(SCSPTR, 0, 0, 0, 0)
|
|
#else
|
|
SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
|
|
#endif
|
|
SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
|
|
#endif
|
|
#endif
|
|
#define sci_in(port, reg) sci_##reg##_in(port)
|
|
#define sci_out(port, reg, value) sci_##reg##_out(port, value)
|
|
|
|
/* H8/300 series SCI pins assignment */
|
|
#if defined(__H8300H__) || defined(__H8300S__)
|
|
static const struct __attribute__((packed)) {
|
|
int port; /* GPIO port no */
|
|
unsigned short rx,tx; /* GPIO bit no */
|
|
} h8300_sci_pins[] = {
|
|
#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
|
|
{ /* SCI0 */
|
|
.port = H8300_GPIO_P9,
|
|
.rx = H8300_GPIO_B2,
|
|
.tx = H8300_GPIO_B0,
|
|
},
|
|
{ /* SCI1 */
|
|
.port = H8300_GPIO_P9,
|
|
.rx = H8300_GPIO_B3,
|
|
.tx = H8300_GPIO_B1,
|
|
},
|
|
{ /* SCI2 */
|
|
.port = H8300_GPIO_PB,
|
|
.rx = H8300_GPIO_B7,
|
|
.tx = H8300_GPIO_B6,
|
|
}
|
|
#elif defined(CONFIG_H8S2678)
|
|
{ /* SCI0 */
|
|
.port = H8300_GPIO_P3,
|
|
.rx = H8300_GPIO_B2,
|
|
.tx = H8300_GPIO_B0,
|
|
},
|
|
{ /* SCI1 */
|
|
.port = H8300_GPIO_P3,
|
|
.rx = H8300_GPIO_B3,
|
|
.tx = H8300_GPIO_B1,
|
|
},
|
|
{ /* SCI2 */
|
|
.port = H8300_GPIO_P5,
|
|
.rx = H8300_GPIO_B1,
|
|
.tx = H8300_GPIO_B0,
|
|
}
|
|
#endif
|
|
};
|
|
#endif
|
|
|
|
#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
|
|
defined(CONFIG_CPU_SUBTYPE_SH7707) || \
|
|
defined(CONFIG_CPU_SUBTYPE_SH7708) || \
|
|
defined(CONFIG_CPU_SUBTYPE_SH7709)
|
|
static inline int sci_rxd_in(struct uart_port *port)
|
|
{
|
|
if (port->mapbase == 0xfffffe80)
|
|
return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */
|
|
return 1;
|
|
}
|
|
#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
|
|
defined(CONFIG_CPU_SUBTYPE_SH7751) || \
|
|
defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
|
|
defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
|
|
defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
|
|
defined(CONFIG_CPU_SUBTYPE_SH7091)
|
|
static inline int sci_rxd_in(struct uart_port *port)
|
|
{
|
|
if (port->mapbase == 0xffe00000)
|
|
return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
|
|
return 1;
|
|
}
|
|
#elif defined(__H8300H__) || defined(__H8300S__)
|
|
static inline int sci_rxd_in(struct uart_port *port)
|
|
{
|
|
int ch = (port->mapbase - SMR0) >> 3;
|
|
return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
|
|
}
|
|
#else /* default case for non-SCI processors */
|
|
static inline int sci_rxd_in(struct uart_port *port)
|
|
{
|
|
return 1;
|
|
}
|
|
#endif
|