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e9b1a4f867
After modifying the QP to the Error state, all RX WR would be completed
with WC in IB_WC_WR_FLUSH_ERR status. Current implementation does not
wait for it is done, but destroy the QP and free the link group directly.
So there is a risk that accessing the freed memory in tasklet context.
Here is a crash example:
BUG: unable to handle page fault for address: ffffffff8f220860
#PF: supervisor write access in kernel mode
#PF: error_code(0x0002) - not-present page
PGD f7300e067 P4D f7300e067 PUD f7300f063 PMD 8c4e45063 PTE 800ffff08c9df060
Oops: 0002 [#1] SMP PTI
CPU: 1 PID: 0 Comm: swapper/1 Kdump: loaded Tainted: G S OE 5.10.0-0607+ #23
Hardware name: Inspur NF5280M4/YZMB-00689-101, BIOS 4.1.20 07/09/2018
RIP: 0010:native_queued_spin_lock_slowpath+0x176/0x1b0
Code: f3 90 48 8b 32 48 85 f6 74 f6 eb d5 c1 ee 12 83 e0 03 83 ee 01 48 c1 e0 05 48 63 f6 48 05 00 c8 02 00 48 03 04 f5 00 09 98 8e <48> 89 10 8b 42 08 85 c0 75 09 f3 90 8b 42 08 85 c0 74 f7 48 8b 32
RSP: 0018:ffffb3b6c001ebd8 EFLAGS: 00010086
RAX: ffffffff8f220860 RBX: 0000000000000246 RCX: 0000000000080000
RDX: ffff91db1f86c800 RSI: 000000000000173c RDI: ffff91db62bace00
RBP: ffff91db62bacc00 R08: 0000000000000000 R09: c00000010000028b
R10: 0000000000055198 R11: ffffb3b6c001ea58 R12: ffff91db80e05010
R13: 000000000000000a R14: 0000000000000006 R15: 0000000000000040
FS: 0000000000000000(0000) GS:ffff91db1f840000(0000) knlGS:0000000000000000
CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
CR2: ffffffff8f220860 CR3: 00000001f9580004 CR4: 00000000003706e0
DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
Call Trace:
<IRQ>
_raw_spin_lock_irqsave+0x30/0x40
mlx5_ib_poll_cq+0x4c/0xc50 [mlx5_ib]
smc_wr_rx_tasklet_fn+0x56/0xa0 [smc]
tasklet_action_common.isra.21+0x66/0x100
__do_softirq+0xd5/0x29c
asm_call_irq_on_stack+0x12/0x20
</IRQ>
do_softirq_own_stack+0x37/0x40
irq_exit_rcu+0x9d/0xa0
sysvec_call_function_single+0x34/0x80
asm_sysvec_call_function_single+0x12/0x20
Fixes: bd4ad57718
("smc: initialize IB transport incl. PD, MR, QP, CQ, event, WR")
Signed-off-by: Yacan Liu <liuyacan@corp.netease.com>
Reviewed-by: Tony Lu <tonylu@linux.alibaba.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
141 lines
4.0 KiB
C
141 lines
4.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Shared Memory Communications over RDMA (SMC-R) and RoCE
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*
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* Work Requests exploiting Infiniband API
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*
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* Copyright IBM Corp. 2016
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*
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* Author(s): Steffen Maier <maier@linux.vnet.ibm.com>
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*/
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#ifndef SMC_WR_H
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#define SMC_WR_H
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#include <linux/atomic.h>
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#include <rdma/ib_verbs.h>
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#include <asm/div64.h>
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#include "smc.h"
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#include "smc_core.h"
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#define SMC_WR_BUF_CNT 16 /* # of ctrl buffers per link */
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#define SMC_WR_TX_WAIT_FREE_SLOT_TIME (10 * HZ)
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#define SMC_WR_TX_SIZE 44 /* actual size of wr_send data (<=SMC_WR_BUF_SIZE) */
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#define SMC_WR_TX_PEND_PRIV_SIZE 32
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struct smc_wr_tx_pend_priv {
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u8 priv[SMC_WR_TX_PEND_PRIV_SIZE];
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};
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typedef void (*smc_wr_tx_handler)(struct smc_wr_tx_pend_priv *,
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struct smc_link *,
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enum ib_wc_status);
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typedef bool (*smc_wr_tx_filter)(struct smc_wr_tx_pend_priv *,
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unsigned long);
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typedef void (*smc_wr_tx_dismisser)(struct smc_wr_tx_pend_priv *);
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struct smc_wr_rx_handler {
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struct hlist_node list; /* hash table collision resolution */
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void (*handler)(struct ib_wc *, void *);
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u8 type;
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};
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/* Only used by RDMA write WRs.
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* All other WRs (CDC/LLC) use smc_wr_tx_send handling WR_ID implicitly
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*/
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static inline long smc_wr_tx_get_next_wr_id(struct smc_link *link)
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{
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return atomic_long_inc_return(&link->wr_tx_id);
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}
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static inline void smc_wr_tx_set_wr_id(atomic_long_t *wr_tx_id, long val)
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{
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atomic_long_set(wr_tx_id, val);
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}
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static inline bool smc_wr_tx_link_hold(struct smc_link *link)
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{
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if (!smc_link_sendable(link))
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return false;
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atomic_inc(&link->wr_tx_refcnt);
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return true;
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}
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static inline void smc_wr_tx_link_put(struct smc_link *link)
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{
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if (atomic_dec_and_test(&link->wr_tx_refcnt))
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wake_up_all(&link->wr_tx_wait);
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}
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static inline void smc_wr_drain_cq(struct smc_link *lnk)
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{
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wait_event(lnk->wr_rx_empty_wait, lnk->wr_rx_id_compl == lnk->wr_rx_id);
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}
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static inline void smc_wr_wakeup_tx_wait(struct smc_link *lnk)
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{
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wake_up_all(&lnk->wr_tx_wait);
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}
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static inline void smc_wr_wakeup_reg_wait(struct smc_link *lnk)
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{
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wake_up(&lnk->wr_reg_wait);
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}
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/* post a new receive work request to fill a completed old work request entry */
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static inline int smc_wr_rx_post(struct smc_link *link)
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{
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int rc;
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u64 wr_id, temp_wr_id;
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u32 index;
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wr_id = ++link->wr_rx_id; /* tasklet context, thus not atomic */
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temp_wr_id = wr_id;
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index = do_div(temp_wr_id, link->wr_rx_cnt);
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link->wr_rx_ibs[index].wr_id = wr_id;
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rc = ib_post_recv(link->roce_qp, &link->wr_rx_ibs[index], NULL);
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return rc;
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}
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int smc_wr_create_link(struct smc_link *lnk);
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int smc_wr_alloc_link_mem(struct smc_link *lnk);
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int smc_wr_alloc_lgr_mem(struct smc_link_group *lgr);
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void smc_wr_free_link(struct smc_link *lnk);
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void smc_wr_free_link_mem(struct smc_link *lnk);
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void smc_wr_free_lgr_mem(struct smc_link_group *lgr);
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void smc_wr_remember_qp_attr(struct smc_link *lnk);
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void smc_wr_remove_dev(struct smc_ib_device *smcibdev);
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void smc_wr_add_dev(struct smc_ib_device *smcibdev);
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int smc_wr_tx_get_free_slot(struct smc_link *link, smc_wr_tx_handler handler,
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struct smc_wr_buf **wr_buf,
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struct smc_rdma_wr **wrs,
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struct smc_wr_tx_pend_priv **wr_pend_priv);
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int smc_wr_tx_get_v2_slot(struct smc_link *link,
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smc_wr_tx_handler handler,
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struct smc_wr_v2_buf **wr_buf,
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struct smc_wr_tx_pend_priv **wr_pend_priv);
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int smc_wr_tx_put_slot(struct smc_link *link,
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struct smc_wr_tx_pend_priv *wr_pend_priv);
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int smc_wr_tx_send(struct smc_link *link,
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struct smc_wr_tx_pend_priv *wr_pend_priv);
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int smc_wr_tx_v2_send(struct smc_link *link,
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struct smc_wr_tx_pend_priv *priv, int len);
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int smc_wr_tx_send_wait(struct smc_link *link, struct smc_wr_tx_pend_priv *priv,
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unsigned long timeout);
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void smc_wr_tx_cq_handler(struct ib_cq *ib_cq, void *cq_context);
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void smc_wr_tx_wait_no_pending_sends(struct smc_link *link);
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int smc_wr_rx_register_handler(struct smc_wr_rx_handler *handler);
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int smc_wr_rx_post_init(struct smc_link *link);
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void smc_wr_rx_cq_handler(struct ib_cq *ib_cq, void *cq_context);
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int smc_wr_reg_send(struct smc_link *link, struct ib_mr *mr);
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#endif /* SMC_WR_H */
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