Vineet Gupta ac4c244d4e ARC: irqflags - Interrupt enabling/disabling at in-core intc ... ARC700 has an in-core intc which provides 2 priorities (a.k.a.) "levels" of interrupts (per IRQ) hencforth referred to as L1/L2 interrupts. CPU flags register STATUS32 has Interrupt Enable bits per level (E1/E2) to globally enable (or disable) all IRQs at a level. Hence the implementation of arch_local_irq_{save,restore,enable,disable}( ) The STATUS32 reg can be r/w only using the AUX Interface of ARC, hence the use of LR/SR instructions. Further, E1/E2 bits in there can only be updated using the FLAG insn. The intc supports 32 interrupts - and per IRQ enabling is controlled by a bit in the AUX_IENABLE register, hence the implmentation of arch_{,un}mask_irq( ) routines. Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Cc: Thomas Gleixner <tglx@linutronix.de>		2013-02-11 20:00:30 +05:30
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arcregs.h	ARC: irqflags - Interrupt enabling/disabling at in-core intc	2013-02-11 20:00:30 +05:30
asm-offsets.h
irqflags.h	ARC: irqflags - Interrupt enabling/disabling at in-core intc	2013-02-11 20:00:30 +05:30
Kbuild	ARC: Build system: Makefiles, Kconfig, Linker script	2013-02-11 20:00:25 +05:30