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abeccee403
Current code has hard coded value written to step enable bits. Now the bits are updated based on how many steps are needed to be configured got from platform data. The user needs to take care not to exceed the count more than 16. While using ADC and TSC one should take care to set this parameter correctly. Sebastian added the common lock and moved the code, that manipulates the steps, from into the mfd module. Signed-off-by: Patil, Rachna <rachna@ti.com> Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
302 lines
7.4 KiB
C
302 lines
7.4 KiB
C
/*
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* TI Touch Screen / ADC MFD driver
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*
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* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/regmap.h>
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#include <linux/mfd/core.h>
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#include <linux/pm_runtime.h>
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#include <linux/mfd/ti_am335x_tscadc.h>
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#include <linux/input/ti_am335x_tsc.h>
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#include <linux/platform_data/ti_am335x_adc.h>
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static unsigned int tscadc_readl(struct ti_tscadc_dev *tsadc, unsigned int reg)
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{
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unsigned int val;
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regmap_read(tsadc->regmap_tscadc, reg, &val);
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return val;
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}
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static void tscadc_writel(struct ti_tscadc_dev *tsadc, unsigned int reg,
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unsigned int val)
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{
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regmap_write(tsadc->regmap_tscadc, reg, val);
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}
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static const struct regmap_config tscadc_regmap_config = {
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.name = "ti_tscadc",
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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};
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void am335x_tsc_se_update(struct ti_tscadc_dev *tsadc)
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{
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tscadc_writel(tsadc, REG_SE, tsadc->reg_se_cache);
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}
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EXPORT_SYMBOL_GPL(am335x_tsc_se_update);
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void am335x_tsc_se_set(struct ti_tscadc_dev *tsadc, u32 val)
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{
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spin_lock(&tsadc->reg_lock);
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tsadc->reg_se_cache |= val;
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spin_unlock(&tsadc->reg_lock);
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am335x_tsc_se_update(tsadc);
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}
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EXPORT_SYMBOL_GPL(am335x_tsc_se_set);
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void am335x_tsc_se_clr(struct ti_tscadc_dev *tsadc, u32 val)
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{
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spin_lock(&tsadc->reg_lock);
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tsadc->reg_se_cache &= ~val;
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spin_unlock(&tsadc->reg_lock);
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am335x_tsc_se_update(tsadc);
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}
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EXPORT_SYMBOL_GPL(am335x_tsc_se_clr);
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static void tscadc_idle_config(struct ti_tscadc_dev *config)
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{
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unsigned int idleconfig;
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idleconfig = STEPCONFIG_YNN | STEPCONFIG_INM_ADCREFM |
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STEPCONFIG_INP_ADCREFM | STEPCONFIG_YPN;
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tscadc_writel(config, REG_IDLECONFIG, idleconfig);
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}
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static int ti_tscadc_probe(struct platform_device *pdev)
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{
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struct ti_tscadc_dev *tscadc;
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struct resource *res;
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struct clk *clk;
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struct mfd_tscadc_board *pdata = pdev->dev.platform_data;
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struct mfd_cell *cell;
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int err, ctrl;
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int clk_value, clock_rate;
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int tsc_wires, adc_channels = 0, total_channels;
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if (!pdata) {
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dev_err(&pdev->dev, "Could not find platform data\n");
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return -EINVAL;
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}
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if (pdata->adc_init)
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adc_channels = pdata->adc_init->adc_channels;
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tsc_wires = pdata->tsc_init->wires;
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total_channels = tsc_wires + adc_channels;
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if (total_channels > 8) {
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dev_err(&pdev->dev, "Number of i/p channels more than 8\n");
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return -EINVAL;
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}
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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dev_err(&pdev->dev, "no memory resource defined.\n");
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return -EINVAL;
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}
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/* Allocate memory for device */
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tscadc = devm_kzalloc(&pdev->dev,
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sizeof(struct ti_tscadc_dev), GFP_KERNEL);
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if (!tscadc) {
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dev_err(&pdev->dev, "failed to allocate memory.\n");
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return -ENOMEM;
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}
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tscadc->dev = &pdev->dev;
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err = platform_get_irq(pdev, 0);
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if (err < 0) {
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dev_err(&pdev->dev, "no irq ID is specified.\n");
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goto ret;
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} else
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tscadc->irq = err;
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res = devm_request_mem_region(&pdev->dev,
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res->start, resource_size(res), pdev->name);
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if (!res) {
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dev_err(&pdev->dev, "failed to reserve registers.\n");
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return -EBUSY;
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}
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tscadc->tscadc_base = devm_ioremap(&pdev->dev,
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res->start, resource_size(res));
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if (!tscadc->tscadc_base) {
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dev_err(&pdev->dev, "failed to map registers.\n");
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return -ENOMEM;
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}
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tscadc->regmap_tscadc = devm_regmap_init_mmio(&pdev->dev,
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tscadc->tscadc_base, &tscadc_regmap_config);
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if (IS_ERR(tscadc->regmap_tscadc)) {
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dev_err(&pdev->dev, "regmap init failed\n");
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err = PTR_ERR(tscadc->regmap_tscadc);
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goto ret;
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}
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spin_lock_init(&tscadc->reg_lock);
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pm_runtime_enable(&pdev->dev);
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pm_runtime_get_sync(&pdev->dev);
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/*
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* The TSC_ADC_Subsystem has 2 clock domains
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* OCP_CLK and ADC_CLK.
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* The ADC clock is expected to run at target of 3MHz,
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* and expected to capture 12-bit data at a rate of 200 KSPS.
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* The TSC_ADC_SS controller design assumes the OCP clock is
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* at least 6x faster than the ADC clock.
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*/
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clk = clk_get(&pdev->dev, "adc_tsc_fck");
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if (IS_ERR(clk)) {
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dev_err(&pdev->dev, "failed to get TSC fck\n");
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err = PTR_ERR(clk);
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goto err_disable_clk;
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}
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clock_rate = clk_get_rate(clk);
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clk_put(clk);
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clk_value = clock_rate / ADC_CLK;
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if (clk_value < MAX_CLK_DIV) {
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dev_err(&pdev->dev, "clock input less than min clock requirement\n");
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err = -EINVAL;
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goto err_disable_clk;
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}
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/* TSCADC_CLKDIV needs to be configured to the value minus 1 */
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clk_value = clk_value - 1;
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tscadc_writel(tscadc, REG_CLKDIV, clk_value);
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/* Set the control register bits */
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ctrl = CNTRLREG_STEPCONFIGWRT |
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CNTRLREG_TSCENB |
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CNTRLREG_STEPID |
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CNTRLREG_4WIRE;
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tscadc_writel(tscadc, REG_CTRL, ctrl);
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/* Set register bits for Idle Config Mode */
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tscadc_idle_config(tscadc);
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/* Enable the TSC module enable bit */
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ctrl = tscadc_readl(tscadc, REG_CTRL);
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ctrl |= CNTRLREG_TSCSSENB;
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tscadc_writel(tscadc, REG_CTRL, ctrl);
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/* TSC Cell */
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cell = &tscadc->cells[TSC_CELL];
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cell->name = "tsc";
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cell->platform_data = &tscadc;
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cell->pdata_size = sizeof(tscadc);
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/* ADC Cell */
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cell = &tscadc->cells[ADC_CELL];
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cell->name = "tiadc";
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cell->platform_data = &tscadc;
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cell->pdata_size = sizeof(tscadc);
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err = mfd_add_devices(&pdev->dev, pdev->id, tscadc->cells,
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TSCADC_CELLS, NULL, 0, NULL);
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if (err < 0)
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goto err_disable_clk;
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device_init_wakeup(&pdev->dev, true);
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platform_set_drvdata(pdev, tscadc);
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return 0;
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err_disable_clk:
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pm_runtime_put_sync(&pdev->dev);
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pm_runtime_disable(&pdev->dev);
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ret:
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return err;
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}
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static int ti_tscadc_remove(struct platform_device *pdev)
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{
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struct ti_tscadc_dev *tscadc = platform_get_drvdata(pdev);
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tscadc_writel(tscadc, REG_SE, 0x00);
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pm_runtime_put_sync(&pdev->dev);
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pm_runtime_disable(&pdev->dev);
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mfd_remove_devices(tscadc->dev);
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return 0;
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}
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#ifdef CONFIG_PM
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static int tscadc_suspend(struct device *dev)
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{
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struct ti_tscadc_dev *tscadc_dev = dev_get_drvdata(dev);
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tscadc_writel(tscadc_dev, REG_SE, 0x00);
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pm_runtime_put_sync(dev);
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return 0;
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}
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static int tscadc_resume(struct device *dev)
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{
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struct ti_tscadc_dev *tscadc_dev = dev_get_drvdata(dev);
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unsigned int restore, ctrl;
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pm_runtime_get_sync(dev);
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/* context restore */
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ctrl = CNTRLREG_STEPCONFIGWRT | CNTRLREG_TSCENB |
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CNTRLREG_STEPID | CNTRLREG_4WIRE;
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tscadc_writel(tscadc_dev, REG_CTRL, ctrl);
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tscadc_idle_config(tscadc_dev);
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am335x_tsc_se_update(tscadc_dev);
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restore = tscadc_readl(tscadc_dev, REG_CTRL);
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tscadc_writel(tscadc_dev, REG_CTRL,
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(restore | CNTRLREG_TSCSSENB));
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return 0;
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}
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static const struct dev_pm_ops tscadc_pm_ops = {
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.suspend = tscadc_suspend,
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.resume = tscadc_resume,
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};
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#define TSCADC_PM_OPS (&tscadc_pm_ops)
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#else
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#define TSCADC_PM_OPS NULL
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#endif
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static struct platform_driver ti_tscadc_driver = {
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.driver = {
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.name = "ti_tscadc",
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.owner = THIS_MODULE,
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.pm = TSCADC_PM_OPS,
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},
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.probe = ti_tscadc_probe,
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.remove = ti_tscadc_remove,
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};
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module_platform_driver(ti_tscadc_driver);
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MODULE_DESCRIPTION("TI touchscreen / ADC MFD controller driver");
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MODULE_AUTHOR("Rachna Patil <rachna@ti.com>");
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MODULE_LICENSE("GPL");
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