Bharat Kumar Gogada ab597d35ef PCI: xilinx-nwl: Add support for Xilinx NWL PCIe Host Controller ... Add PCIe Root Port driver for Xilinx PCIe NWL bridge IP. [bhelgaas: wait for link like dw_pcie_wait_for_link(), simplify bitmap error path, typos, whitespace, fold in Dan Carpenter's PTR_ERR() fix] Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Rob Herring <robh@kernel.org>		2016-03-11 12:42:31 -06:00
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bindings	PCI: xilinx-nwl: Add support for Xilinx NWL PCIe Host Controller	2016-03-11 12:42:31 -06:00
00-INDEX
booting-without-of.txt	ARM: 8354/1: Documentation: devicetree: root node serial-number property documentation	2015-05-08 10:42:34 +01:00
changesets.txt
dynamic-resolution-notes.txt
of_unittest.txt	Documentation: rename of_selftest.txt to of_unittest.txt	2015-03-25 00:50:53 -05:00
overlay-notes.txt	Documentation: devicetree: Fix double words in Doumentation/devicetree	2015-01-28 15:13:11 -07:00
todo.txt
usage-model.txt