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f1afb360b6
bitfield.h is not explicitly included but it is required for FIELD_PREP
to be expanded by the preprocessor. If it is not implicitly included,
there will be a compiler error (as seen with ARCH=hexagon allmodconfig):
sound/soc/fsl/lpc3xxx-i2s.c:169:10: error: call to undeclared function 'FIELD_PREP'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
169 | tmp |= LPC3XXX_I2S_WW8 | LPC3XXX_I2S_WS_HP(LPC3XXX_I2S_WW8_HP);
| ^
sound/soc/fsl/lpc3xxx-i2s.h:42:30: note: expanded from macro 'LPC3XXX_I2S_WW8'
42 | #define LPC3XXX_I2S_WW8 FIELD_PREP(0x3, 0) /* Word width is 8bit */
| ^
sound/soc/fsl/lpc3xxx-i2s.c:205:34: error: call to undeclared function 'FIELD_PREP'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
205 | LPC3XXX_I2S_DMA1_TX_EN | LPC3XXX_I2S_DMA0_TX_DEPTH(4));
| ^
sound/soc/fsl/lpc3xxx-i2s.h:65:38: note: expanded from macro 'LPC3XXX_I2S_DMA0_TX_DEPTH'
65 | #define LPC3XXX_I2S_DMA0_TX_DEPTH(s) FIELD_PREP(0xF0000, s) /* Set the DMA1 TX Request level */
| ^
sound/soc/fsl/lpc3xxx-i2s.c:210:34: error: call to undeclared function 'FIELD_PREP'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
210 | LPC3XXX_I2S_DMA0_RX_EN | LPC3XXX_I2S_DMA1_RX_DEPTH(4));
| ^
sound/soc/fsl/lpc3xxx-i2s.h:70:38: note: expanded from macro 'LPC3XXX_I2S_DMA1_RX_DEPTH'
70 | #define LPC3XXX_I2S_DMA1_RX_DEPTH(s) FIELD_PREP(0x700, s) /* Set the DMA1 RX Request level */
| ^
Include bitfield.h explicitly, so that FIELD_PREP is always expanded,
clearing up the compiler error.
Fixes: 0959de657a ("ASoC: fsl: Add i2s and pcm drivers for LPC32xx CPUs")
Signed-off-by: Nathan Chancellor <nathan@kernel.org>
Link: https://patch.msgid.link/20240701-lpc32xx-asoc-fix-include-for-field_prep-v1-1-0c5d7f71921b@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
81 lines
3.3 KiB
C
81 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Author: Kevin Wells <kevin.wells@nxp.com>
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*
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* Copyright (C) 2008 NXP Semiconductors
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* Copyright 2023 Timesys Corporation <piotr.wojtaszczyk@timesys.com>
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*/
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#ifndef __SOUND_SOC_LPC3XXX_I2S_H
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#define __SOUND_SOC_LPC3XXX_I2S_H
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#include <linux/bitfield.h>
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#include <linux/types.h>
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#include <linux/regmap.h>
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struct lpc3xxx_i2s_info {
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struct device *dev;
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struct clk *clk;
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struct mutex lock; /* To serialize user-space access */
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struct regmap *regs;
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u32 streams_in_use;
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u32 clkrate;
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int freq;
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struct snd_dmaengine_dai_dma_data playback_dma_config;
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struct snd_dmaengine_dai_dma_data capture_dma_config;
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};
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int lpc3xxx_pcm_register(struct platform_device *pdev);
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/* I2S controller register offsets */
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#define LPC3XXX_REG_I2S_DAO 0x00
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#define LPC3XXX_REG_I2S_DAI 0x04
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#define LPC3XXX_REG_I2S_TX_FIFO 0x08
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#define LPC3XXX_REG_I2S_RX_FIFO 0x0C
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#define LPC3XXX_REG_I2S_STAT 0x10
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#define LPC3XXX_REG_I2S_DMA0 0x14
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#define LPC3XXX_REG_I2S_DMA1 0x18
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#define LPC3XXX_REG_I2S_IRQ 0x1C
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#define LPC3XXX_REG_I2S_TX_RATE 0x20
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#define LPC3XXX_REG_I2S_RX_RATE 0x24
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/* i2s_daO i2s_dai register definitions */
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#define LPC3XXX_I2S_WW8 FIELD_PREP(0x3, 0) /* Word width is 8bit */
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#define LPC3XXX_I2S_WW16 FIELD_PREP(0x3, 1) /* Word width is 16bit */
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#define LPC3XXX_I2S_WW32 FIELD_PREP(0x3, 3) /* Word width is 32bit */
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#define LPC3XXX_I2S_MONO BIT(2) /* Mono */
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#define LPC3XXX_I2S_STOP BIT(3) /* Stop, diables the access to FIFO, mutes the channel */
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#define LPC3XXX_I2S_RESET BIT(4) /* Reset the channel */
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#define LPC3XXX_I2S_WS_SEL BIT(5) /* Channel Master(0) or slave(1) mode select */
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#define LPC3XXX_I2S_WS_HP(s) FIELD_PREP(0x7FC0, s) /* Word select half period - 1 */
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#define LPC3XXX_I2S_MUTE BIT(15) /* Mute the channel, Transmit channel only */
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#define LPC3XXX_I2S_WW32_HP 0x1f /* Word select half period for 32bit word width */
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#define LPC3XXX_I2S_WW16_HP 0x0f /* Word select half period for 16bit word width */
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#define LPC3XXX_I2S_WW8_HP 0x7 /* Word select half period for 8bit word width */
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/* i2s_stat register definitions */
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#define LPC3XXX_I2S_IRQ_STAT BIT(0)
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#define LPC3XXX_I2S_DMA0_REQ BIT(1)
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#define LPC3XXX_I2S_DMA1_REQ BIT(2)
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/* i2s_dma0 Configuration register definitions */
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#define LPC3XXX_I2S_DMA0_RX_EN BIT(0) /* Enable RX DMA1 */
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#define LPC3XXX_I2S_DMA0_TX_EN BIT(1) /* Enable TX DMA1 */
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#define LPC3XXX_I2S_DMA0_RX_DEPTH(s) FIELD_PREP(0xF00, s) /* Set the DMA1 RX Request level */
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#define LPC3XXX_I2S_DMA0_TX_DEPTH(s) FIELD_PREP(0xF0000, s) /* Set the DMA1 TX Request level */
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/* i2s_dma1 Configuration register definitions */
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#define LPC3XXX_I2S_DMA1_RX_EN BIT(0) /* Enable RX DMA1 */
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#define LPC3XXX_I2S_DMA1_TX_EN BIT(1) /* Enable TX DMA1 */
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#define LPC3XXX_I2S_DMA1_RX_DEPTH(s) FIELD_PREP(0x700, s) /* Set the DMA1 RX Request level */
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#define LPC3XXX_I2S_DMA1_TX_DEPTH(s) FIELD_PREP(0x70000, s) /* Set the DMA1 TX Request level */
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/* i2s_irq register definitions */
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#define LPC3XXX_I2S_RX_IRQ_EN BIT(0) /* Enable RX IRQ */
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#define LPC3XXX_I2S_TX_IRQ_EN BIT(1) /* Enable TX IRQ */
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#define LPC3XXX_I2S_IRQ_RX_DEPTH(s) FIELD_PREP(0xFF00, s) /* valid values ar 0 to 7 */
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#define LPC3XXX_I2S_IRQ_TX_DEPTH(s) FIELD_PREP(0xFF0000, s) /* valid values ar 0 to 7 */
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#endif
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