linux/scripts/mkmakefile
Milton Miller 0b35786d77 kbuild: call make once for all targets when O=.. is used
Change the invocations of make in the output directory Makefile and the
main Makefile for separate object trees to pass all goals to one $(MAKE)
via a new phony target "sub-make" and the existing target _all.

When compiling with separate object directories, a separate make is called
in the context of another directory (from the output directory the main
Makefile is called, the Makefile is then restarted with current directory
set to the object tree).  Before this patch, when multiple make command
goals are specified, each target results in a separate make invocation.
With make -j, these invocations may run in parallel, resulting in multiple
commands running in the same directory clobbering each others results.

I did not try to address make -j for mixed dot-config and no-dot-config
targets.  Because the order does matter, a solution was not obvious.
Perhaps a simple check for MAKEFLAGS having -j and refusing to run would
be appropriate.

Signed-off-by: Milton Miller <miltonm@bga.com>
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
2007-10-12 21:20:32 +02:00

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#!/bin/sh
# Generates a small Makefile used in the root of the output
# directory, to allow make to be started from there.
# The Makefile also allow for more convinient build of external modules
# Usage
# $1 - Kernel src directory
# $2 - Output directory
# $3 - version
# $4 - patchlevel
test ! -r $2/Makefile -o -O $2/Makefile || exit 0
echo " GEN $2/Makefile"
cat << EOF > $2/Makefile
# Automatically generated by $0: don't edit
VERSION = $3
PATCHLEVEL = $4
KERNELSRC := $1
KERNELOUTPUT := $2
MAKEFLAGS += --no-print-directory
.PHONY: all \$(MAKECMDGOALS)
all := \$(filter-out all Makefile,\$(MAKECMDGOALS))
all:
\$(MAKE) -C \$(KERNELSRC) O=\$(KERNELOUTPUT) \$(all)
Makefile:;
\$(all) %/: all
@:
EOF