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c78a41fc04
As a final bit of preparation for converting to ARCH_MULTIPLATFORM, change the interrupt handling for s3c24xx to use sparse IRQs. Since the number of possible interrupts is already fixed and relatively small per chip, just make it use all legacy interrupts preallocated using the .nr_irqs field in the machine descriptor, rather than actually allocating domains on the fly. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
231 lines
5.6 KiB
C
231 lines
5.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// Copyright 2008 Openmoko, Inc.
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// Copyright 2008 Simtec Electronics
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// Ben Dooks <ben@simtec.co.uk>
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// http://armlinux.simtec.co.uk/
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// Copyright 2009 Kwangwoo Lee
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// Kwangwoo Lee <kwangwoo.lee@gmail.com>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <linux/timer.h>
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#include <linux/init.h>
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#include <linux/serial_core.h>
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#include <linux/serial_s3c.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/i2c.h>
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#include <linux/fb.h>
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#include <linux/gpio.h>
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#include <linux/delay.h>
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#include <linux/dm9000.h>
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#include <video/platform_lcd.h>
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#include <video/samsung_fimd.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/irq.h>
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#include "map.h"
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#include <asm/irq.h>
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#include <asm/mach-types.h>
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#include <linux/platform_data/i2c-s3c2410.h>
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#include "fb.h"
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#include "devs.h"
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#include "cpu.h"
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#include "irqs.h"
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#include "regs-gpio.h"
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#include "gpio-samsung.h"
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#include "s3c64xx.h"
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#include "regs-modem-s3c64xx.h"
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/* DM9000 */
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#define ANW6410_PA_DM9000 (0x18000000)
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/* A hardware buffer to control external devices is mapped at 0x30000000.
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* It can not be read. So current status must be kept in anw6410_extdev_status.
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*/
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#define ANW6410_VA_EXTDEV S3C_ADDR(0x02000000)
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#define ANW6410_PA_EXTDEV (0x30000000)
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#define ANW6410_EN_DM9000 (1<<11)
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#define ANW6410_EN_LCD (1<<14)
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static __u32 anw6410_extdev_status;
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static struct s3c2410_uartcfg anw6410_uartcfgs[] __initdata = {
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[0] = {
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.hwport = 0,
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.flags = 0,
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.ucon = 0x3c5,
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.ulcon = 0x03,
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.ufcon = 0x51,
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},
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[1] = {
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.hwport = 1,
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.flags = 0,
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.ucon = 0x3c5,
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.ulcon = 0x03,
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.ufcon = 0x51,
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},
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};
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/* framebuffer and LCD setup. */
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static void __init anw6410_lcd_mode_set(void)
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{
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u32 tmp;
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/* set the LCD type */
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tmp = __raw_readl(S3C64XX_SPCON);
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tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
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tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
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__raw_writel(tmp, S3C64XX_SPCON);
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/* remove the LCD bypass */
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tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
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tmp &= ~MIFPCON_LCD_BYPASS;
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__raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
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}
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/* GPF1 = LCD panel power
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* GPF4 = LCD backlight control
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*/
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static void anw6410_lcd_power_set(struct plat_lcd_data *pd,
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unsigned int power)
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{
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if (power) {
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anw6410_extdev_status |= (ANW6410_EN_LCD << 16);
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__raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
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gpio_direction_output(S3C64XX_GPF(1), 1);
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gpio_direction_output(S3C64XX_GPF(4), 1);
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} else {
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anw6410_extdev_status &= ~(ANW6410_EN_LCD << 16);
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__raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
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gpio_direction_output(S3C64XX_GPF(1), 0);
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gpio_direction_output(S3C64XX_GPF(4), 0);
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}
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}
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static struct plat_lcd_data anw6410_lcd_power_data = {
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.set_power = anw6410_lcd_power_set,
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};
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static struct platform_device anw6410_lcd_powerdev = {
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.name = "platform-lcd",
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.dev.parent = &s3c_device_fb.dev,
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.dev.platform_data = &anw6410_lcd_power_data,
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};
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static struct s3c_fb_pd_win anw6410_fb_win0 = {
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.max_bpp = 32,
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.default_bpp = 16,
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.xres = 800,
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.yres = 480,
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};
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static struct fb_videomode anw6410_lcd_timing = {
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.left_margin = 8,
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.right_margin = 13,
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.upper_margin = 7,
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.lower_margin = 5,
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.hsync_len = 3,
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.vsync_len = 1,
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.xres = 800,
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.yres = 480,
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};
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/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
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static struct s3c_fb_platdata anw6410_lcd_pdata __initdata = {
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.setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
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.vtiming = &anw6410_lcd_timing,
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.win[0] = &anw6410_fb_win0,
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.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
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.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
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};
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/* DM9000AEP 10/100 ethernet controller */
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static void __init anw6410_dm9000_enable(void)
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{
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anw6410_extdev_status |= (ANW6410_EN_DM9000 << 16);
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__raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
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}
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static struct resource anw6410_dm9000_resource[] = {
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[0] = DEFINE_RES_MEM(ANW6410_PA_DM9000, 4),
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[1] = DEFINE_RES_MEM(ANW6410_PA_DM9000 + 4, 501),
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[2] = DEFINE_RES_NAMED(IRQ_EINT(15), 1, NULL, IORESOURCE_IRQ \
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| IRQF_TRIGGER_HIGH),
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};
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static struct dm9000_plat_data anw6410_dm9000_pdata = {
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.flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
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/* dev_addr can be set to provide hwaddr. */
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};
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static struct platform_device anw6410_device_eth = {
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.name = "dm9000",
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.id = -1,
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.num_resources = ARRAY_SIZE(anw6410_dm9000_resource),
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.resource = anw6410_dm9000_resource,
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.dev = {
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.platform_data = &anw6410_dm9000_pdata,
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},
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};
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static struct map_desc anw6410_iodesc[] __initdata = {
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{
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.virtual = (unsigned long)ANW6410_VA_EXTDEV,
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.pfn = __phys_to_pfn(ANW6410_PA_EXTDEV),
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.length = SZ_64K,
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.type = MT_DEVICE,
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},
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};
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static struct platform_device *anw6410_devices[] __initdata = {
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&s3c_device_fb,
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&anw6410_lcd_powerdev,
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&anw6410_device_eth,
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};
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static void __init anw6410_map_io(void)
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{
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s3c64xx_init_io(anw6410_iodesc, ARRAY_SIZE(anw6410_iodesc));
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s3c64xx_set_xtal_freq(12000000);
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s3c24xx_init_uarts(anw6410_uartcfgs, ARRAY_SIZE(anw6410_uartcfgs));
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s3c64xx_set_timer_source(S3C64XX_PWM3, S3C64XX_PWM4);
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anw6410_lcd_mode_set();
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}
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static void __init anw6410_machine_init(void)
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{
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s3c_fb_set_platdata(&anw6410_lcd_pdata);
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gpio_request(S3C64XX_GPF(1), "panel power");
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gpio_request(S3C64XX_GPF(4), "LCD backlight");
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anw6410_dm9000_enable();
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platform_add_devices(anw6410_devices, ARRAY_SIZE(anw6410_devices));
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}
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MACHINE_START(ANW6410, "A&W6410")
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/* Maintainer: Kwangwoo Lee <kwangwoo.lee@gmail.com> */
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.atag_offset = 0x100,
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.nr_irqs = S3C64XX_NR_IRQS,
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.init_irq = s3c6410_init_irq,
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.map_io = anw6410_map_io,
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.init_machine = anw6410_machine_init,
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.init_time = s3c64xx_timer_init,
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MACHINE_END
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