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dd006da216
The page size and the number of translation levels, and hence the supported virtual address range, are build-time configurables on arm64 whose optimal values are use case dependent. However, in the current implementation, if the system's RAM is located at a very high offset, the virtual address range needs to reflect that merely because the identity mapping, which is only used to enable or disable the MMU, requires the extended virtual range to map the physical memory at an equal virtual offset. This patch relaxes that requirement, by increasing the number of translation levels for the identity mapping only, and only when actually needed, i.e., when system RAM's offset is found to be out of reach at runtime. Tested-by: Laura Abbott <lauraa@codeaurora.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
265 lines
5.9 KiB
ArmAsm
265 lines
5.9 KiB
ArmAsm
/*
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* Based on arch/arm/mm/proc.S
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*
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* Copyright (C) 2001 Deep Blue Solutions Ltd.
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* Copyright (C) 2012 ARM Ltd.
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* Author: Catalin Marinas <catalin.marinas@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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#include <asm/hwcap.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#include "proc-macros.S"
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#ifdef CONFIG_ARM64_64K_PAGES
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#define TCR_TG_FLAGS TCR_TG0_64K | TCR_TG1_64K
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#else
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#define TCR_TG_FLAGS TCR_TG0_4K | TCR_TG1_4K
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#endif
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#ifdef CONFIG_SMP
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#define TCR_SMP_FLAGS TCR_SHARED
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#else
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#define TCR_SMP_FLAGS 0
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#endif
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/* PTWs cacheable, inner/outer WBWA */
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#define TCR_CACHE_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA
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#define MAIR(attr, mt) ((attr) << ((mt) * 8))
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/*
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* cpu_cache_off()
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*
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* Turn the CPU D-cache off.
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*/
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ENTRY(cpu_cache_off)
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mrs x0, sctlr_el1
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bic x0, x0, #1 << 2 // clear SCTLR.C
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msr sctlr_el1, x0
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isb
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ret
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ENDPROC(cpu_cache_off)
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/*
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* cpu_reset(loc)
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*
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* Perform a soft reset of the system. Put the CPU into the same state
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* as it would be if it had been reset, and branch to what would be the
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* reset vector. It must be executed with the flat identity mapping.
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*
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* - loc - location to jump to for soft reset
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*/
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.align 5
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ENTRY(cpu_reset)
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mrs x1, sctlr_el1
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bic x1, x1, #1
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msr sctlr_el1, x1 // disable the MMU
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isb
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ret x0
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ENDPROC(cpu_reset)
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ENTRY(cpu_soft_restart)
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/* Save address of cpu_reset() and reset address */
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mov x19, x0
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mov x20, x1
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/* Turn D-cache off */
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bl cpu_cache_off
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/* Push out all dirty data, and ensure cache is empty */
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bl flush_cache_all
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mov x0, x20
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ret x19
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ENDPROC(cpu_soft_restart)
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/*
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* cpu_do_idle()
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*
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* Idle the processor (wait for interrupt).
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*/
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ENTRY(cpu_do_idle)
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dsb sy // WFI may enter a low-power mode
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wfi
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ret
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ENDPROC(cpu_do_idle)
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#ifdef CONFIG_CPU_PM
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/**
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* cpu_do_suspend - save CPU registers context
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*
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* x0: virtual address of context pointer
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*/
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ENTRY(cpu_do_suspend)
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mrs x2, tpidr_el0
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mrs x3, tpidrro_el0
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mrs x4, contextidr_el1
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mrs x5, mair_el1
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mrs x6, cpacr_el1
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mrs x7, ttbr1_el1
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mrs x8, tcr_el1
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mrs x9, vbar_el1
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mrs x10, mdscr_el1
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mrs x11, oslsr_el1
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mrs x12, sctlr_el1
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stp x2, x3, [x0]
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stp x4, x5, [x0, #16]
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stp x6, x7, [x0, #32]
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stp x8, x9, [x0, #48]
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stp x10, x11, [x0, #64]
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str x12, [x0, #80]
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ret
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ENDPROC(cpu_do_suspend)
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/**
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* cpu_do_resume - restore CPU register context
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*
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* x0: Physical address of context pointer
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* x1: ttbr0_el1 to be restored
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*
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* Returns:
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* sctlr_el1 value in x0
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*/
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ENTRY(cpu_do_resume)
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/*
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* Invalidate local tlb entries before turning on MMU
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*/
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tlbi vmalle1
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ldp x2, x3, [x0]
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ldp x4, x5, [x0, #16]
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ldp x6, x7, [x0, #32]
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ldp x8, x9, [x0, #48]
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ldp x10, x11, [x0, #64]
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ldr x12, [x0, #80]
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msr tpidr_el0, x2
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msr tpidrro_el0, x3
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msr contextidr_el1, x4
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msr mair_el1, x5
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msr cpacr_el1, x6
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msr ttbr0_el1, x1
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msr ttbr1_el1, x7
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tcr_set_idmap_t0sz x8, x7
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msr tcr_el1, x8
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msr vbar_el1, x9
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msr mdscr_el1, x10
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/*
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* Restore oslsr_el1 by writing oslar_el1
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*/
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ubfx x11, x11, #1, #1
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msr oslar_el1, x11
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mov x0, x12
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dsb nsh // Make sure local tlb invalidation completed
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isb
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ret
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ENDPROC(cpu_do_resume)
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#endif
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/*
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* cpu_do_switch_mm(pgd_phys, tsk)
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*
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* Set the translation table base pointer to be pgd_phys.
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*
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* - pgd_phys - physical address of new TTB
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*/
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ENTRY(cpu_do_switch_mm)
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mmid w1, x1 // get mm->context.id
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bfi x0, x1, #48, #16 // set the ASID
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msr ttbr0_el1, x0 // set TTBR0
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isb
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ret
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ENDPROC(cpu_do_switch_mm)
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.section ".text.init", #alloc, #execinstr
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/*
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* __cpu_setup
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*
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* Initialise the processor for turning the MMU on. Return in x0 the
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* value of the SCTLR_EL1 register.
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*/
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ENTRY(__cpu_setup)
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ic iallu // I+BTB cache invalidate
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tlbi vmalle1is // invalidate I + D TLBs
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dsb ish
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mov x0, #3 << 20
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msr cpacr_el1, x0 // Enable FP/ASIMD
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msr mdscr_el1, xzr // Reset mdscr_el1
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/*
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* Memory region attributes for LPAE:
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*
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* n = AttrIndx[2:0]
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* n MAIR
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* DEVICE_nGnRnE 000 00000000
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* DEVICE_nGnRE 001 00000100
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* DEVICE_GRE 010 00001100
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* NORMAL_NC 011 01000100
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* NORMAL 100 11111111
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*/
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ldr x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \
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MAIR(0x04, MT_DEVICE_nGnRE) | \
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MAIR(0x0c, MT_DEVICE_GRE) | \
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MAIR(0x44, MT_NORMAL_NC) | \
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MAIR(0xff, MT_NORMAL)
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msr mair_el1, x5
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/*
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* Prepare SCTLR
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*/
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adr x5, crval
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ldp w5, w6, [x5]
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mrs x0, sctlr_el1
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bic x0, x0, x5 // clear bits
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orr x0, x0, x6 // set bits
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/*
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* Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for
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* both user and kernel.
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*/
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ldr x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \
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TCR_TG_FLAGS | TCR_ASID16 | TCR_TBI0
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tcr_set_idmap_t0sz x10, x9
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/*
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* Read the PARange bits from ID_AA64MMFR0_EL1 and set the IPS bits in
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* TCR_EL1.
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*/
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mrs x9, ID_AA64MMFR0_EL1
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bfi x10, x9, #32, #3
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msr tcr_el1, x10
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ret // return to head.S
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ENDPROC(__cpu_setup)
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/*
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* We set the desired value explicitly, including those of the
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* reserved bits. The values of bits EE & E0E were set early in
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* el2_setup, which are left untouched below.
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*
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* n n T
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* U E WT T UD US IHBS
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* CE0 XWHW CZ ME TEEA S
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* .... .IEE .... NEAI TE.I ..AD DEN0 ACAM
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* 0011 0... 1101 ..0. ..0. 10.. .0.. .... < hardware reserved
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* .... .1.. .... 01.1 11.1 ..01 0.01 1101 < software settings
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*/
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.type crval, #object
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crval:
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.word 0xfcffffff // clear
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.word 0x34d5d91d // set
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