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7e23620dff
Add MT8186 vdec clock controller which provide clock gate control for video decoder. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220409132251.31725-12-chun-jie.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
89 lines
2.4 KiB
C
89 lines
2.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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//
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// Copyright (c) 2022 MediaTek Inc.
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// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#include <dt-bindings/clock/mt8186-clk.h>
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static const struct mtk_gate_regs vdec0_cg_regs = {
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.set_ofs = 0x0,
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.clr_ofs = 0x4,
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.sta_ofs = 0x0,
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};
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static const struct mtk_gate_regs vdec1_cg_regs = {
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.set_ofs = 0x190,
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.clr_ofs = 0x190,
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.sta_ofs = 0x190,
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};
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static const struct mtk_gate_regs vdec2_cg_regs = {
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.set_ofs = 0x200,
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.clr_ofs = 0x204,
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.sta_ofs = 0x200,
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};
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static const struct mtk_gate_regs vdec3_cg_regs = {
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.set_ofs = 0x8,
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.clr_ofs = 0xc,
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.sta_ofs = 0x8,
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};
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#define GATE_VDEC0(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
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#define GATE_VDEC1(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
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#define GATE_VDEC2(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
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#define GATE_VDEC3(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &vdec3_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
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static const struct mtk_gate vdec_clks[] = {
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/* VDEC0 */
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GATE_VDEC0(CLK_VDEC_CKEN, "vdec_cken", "top_vdec", 0),
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GATE_VDEC0(CLK_VDEC_ACTIVE, "vdec_active", "top_vdec", 4),
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GATE_VDEC0(CLK_VDEC_CKEN_ENG, "vdec_cken_eng", "top_vdec", 8),
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/* VDEC1 */
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GATE_VDEC1(CLK_VDEC_MINI_MDP_CKEN_CFG_RG, "vdec_mini_mdp_cken_cfg_rg", "top_vdec", 0),
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/* VDEC2 */
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GATE_VDEC2(CLK_VDEC_LAT_CKEN, "vdec_lat_cken", "top_vdec", 0),
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GATE_VDEC2(CLK_VDEC_LAT_ACTIVE, "vdec_lat_active", "top_vdec", 4),
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GATE_VDEC2(CLK_VDEC_LAT_CKEN_ENG, "vdec_lat_cken_eng", "top_vdec", 8),
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/* VDEC3 */
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GATE_VDEC3(CLK_VDEC_LARB1_CKEN, "vdec_larb1_cken", "top_vdec", 0),
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};
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static const struct mtk_clk_desc vdec_desc = {
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.clks = vdec_clks,
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.num_clks = ARRAY_SIZE(vdec_clks),
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};
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static const struct of_device_id of_match_clk_mt8186_vdec[] = {
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{
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.compatible = "mediatek,mt8186-vdecsys",
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.data = &vdec_desc,
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}, {
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/* sentinel */
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}
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};
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static struct platform_driver clk_mt8186_vdec_drv = {
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.probe = mtk_clk_simple_probe,
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.remove = mtk_clk_simple_remove,
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.driver = {
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.name = "clk-mt8186-vdec",
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.of_match_table = of_match_clk_mt8186_vdec,
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},
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};
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builtin_platform_driver(clk_mt8186_vdec_drv);
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