mirror of
https://github.com/torvalds/linux.git
synced 2024-11-12 15:11:50 +00:00
13731d862c
Stephen Warren reported the recent commit 78506f2 (add support for
extended FIFO-size of PL011-r1p5) breaks the serial port on the
BCM2835 ARM SoC.
A UART compatible with the ARM PL011-r1p5 should have 32-deep FIFOs.
The BCM2835 UART just looks like an ARM PL011-r1p5, but has 16-deep
FIFOs just like PL011-r1p4 or earlier revisions. As a workaround for
this compatibility issue, this patch overrides the HW UART periphid
register values with the actually compatible UART periphid 0x00241011
(r1p3 or r1p4).
Reported-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Jongsung Kim <neidhard.kim@lge.com>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
135 lines
2.8 KiB
Plaintext
135 lines
2.8 KiB
Plaintext
/include/ "skeleton.dtsi"
|
|
|
|
/ {
|
|
compatible = "brcm,bcm2835";
|
|
model = "BCM2835";
|
|
interrupt-parent = <&intc>;
|
|
|
|
chosen {
|
|
bootargs = "earlyprintk console=ttyAMA0";
|
|
};
|
|
|
|
soc {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x7e000000 0x20000000 0x02000000>;
|
|
|
|
timer {
|
|
compatible = "brcm,bcm2835-system-timer";
|
|
reg = <0x7e003000 0x1000>;
|
|
interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
|
|
clock-frequency = <1000000>;
|
|
};
|
|
|
|
intc: interrupt-controller {
|
|
compatible = "brcm,bcm2835-armctrl-ic";
|
|
reg = <0x7e00b200 0x200>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
watchdog {
|
|
compatible = "brcm,bcm2835-pm-wdt";
|
|
reg = <0x7e100000 0x28>;
|
|
};
|
|
|
|
rng {
|
|
compatible = "brcm,bcm2835-rng";
|
|
reg = <0x7e104000 0x10>;
|
|
};
|
|
|
|
uart@20201000 {
|
|
compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
|
|
reg = <0x7e201000 0x1000>;
|
|
interrupts = <2 25>;
|
|
clock-frequency = <3000000>;
|
|
arm,primecell-periphid = <0x00241011>;
|
|
};
|
|
|
|
gpio: gpio {
|
|
compatible = "brcm,bcm2835-gpio";
|
|
reg = <0x7e200000 0xb4>;
|
|
/*
|
|
* The GPIO IP block is designed for 3 banks of GPIOs.
|
|
* Each bank has a GPIO interrupt for itself.
|
|
* There is an overall "any bank" interrupt.
|
|
* In order, these are GIC interrupts 17, 18, 19, 20.
|
|
* Since the BCM2835 only has 2 banks, the 2nd bank
|
|
* interrupt output appears to be mirrored onto the
|
|
* 3rd bank's interrupt signal.
|
|
* So, a bank0 interrupt shows up on 17, 20, and
|
|
* a bank1 interrupt shows up on 18, 19, 20!
|
|
*/
|
|
interrupts = <2 17>, <2 18>, <2 19>, <2 20>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
spi: spi@20204000 {
|
|
compatible = "brcm,bcm2835-spi";
|
|
reg = <0x7e204000 0x1000>;
|
|
interrupts = <2 22>;
|
|
clocks = <&clk_spi>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@20205000 {
|
|
compatible = "brcm,bcm2835-i2c";
|
|
reg = <0x7e205000 0x1000>;
|
|
interrupts = <2 21>;
|
|
clocks = <&clk_i2c>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@20804000 {
|
|
compatible = "brcm,bcm2835-i2c";
|
|
reg = <0x7e804000 0x1000>;
|
|
interrupts = <2 21>;
|
|
clocks = <&clk_i2c>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhci: sdhci {
|
|
compatible = "brcm,bcm2835-sdhci";
|
|
reg = <0x7e300000 0x100>;
|
|
interrupts = <2 30>;
|
|
clocks = <&clk_mmc>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
clocks {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
clk_mmc: mmc {
|
|
compatible = "fixed-clock";
|
|
reg = <0>;
|
|
#clock-cells = <0>;
|
|
clock-frequency = <100000000>;
|
|
};
|
|
|
|
clk_i2c: i2c {
|
|
compatible = "fixed-clock";
|
|
reg = <1>;
|
|
#clock-cells = <0>;
|
|
clock-frequency = <250000000>;
|
|
};
|
|
|
|
clk_spi: spi {
|
|
compatible = "fixed-clock";
|
|
reg = <2>;
|
|
#clock-cells = <0>;
|
|
clock-frequency = <250000000>;
|
|
};
|
|
};
|
|
};
|