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6c320fef58
It may not be necessary to fail in certain cases (such as failing to idle) on module unload, whereas on suspend it's important to ensure a consistent state can be restored on resume. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
312 lines
8.4 KiB
C
312 lines
8.4 KiB
C
/*
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* Copyright 2011 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "drmP.h"
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#include "nouveau_drv.h"
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#include "nouveau_ramht.h"
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struct nv40_mpeg_engine {
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struct nouveau_exec_engine base;
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};
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static int
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nv40_mpeg_context_new(struct nouveau_channel *chan, int engine)
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{
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpuobj *ctx = NULL;
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unsigned long flags;
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int ret;
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NV_DEBUG(dev, "ch%d\n", chan->id);
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ret = nouveau_gpuobj_new(dev, NULL, 264 * 4, 16, NVOBJ_FLAG_ZERO_ALLOC |
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NVOBJ_FLAG_ZERO_FREE, &ctx);
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if (ret)
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return ret;
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nv_wo32(ctx, 0x78, 0x02001ec1);
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spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
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nv_mask(dev, 0x002500, 0x00000001, 0x00000000);
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if ((nv_rd32(dev, 0x003204) & 0x1f) == chan->id)
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nv_wr32(dev, 0x00330c, ctx->pinst >> 4);
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nv_wo32(chan->ramfc, 0x54, ctx->pinst >> 4);
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nv_mask(dev, 0x002500, 0x00000001, 0x00000001);
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spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
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chan->engctx[engine] = ctx;
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return 0;
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}
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static void
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nv40_mpeg_context_del(struct nouveau_channel *chan, int engine)
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{
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struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
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struct nouveau_gpuobj *ctx = chan->engctx[engine];
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struct drm_device *dev = chan->dev;
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unsigned long flags;
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u32 inst = 0x80000000 | (ctx->pinst >> 4);
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spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
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nv_mask(dev, 0x00b32c, 0x00000001, 0x00000000);
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if (nv_rd32(dev, 0x00b318) == inst)
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nv_mask(dev, 0x00b318, 0x80000000, 0x00000000);
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nv_mask(dev, 0x00b32c, 0x00000001, 0x00000001);
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spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
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nouveau_gpuobj_ref(NULL, &ctx);
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chan->engctx[engine] = NULL;
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}
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static int
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nv40_mpeg_object_new(struct nouveau_channel *chan, int engine,
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u32 handle, u16 class)
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{
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struct drm_device *dev = chan->dev;
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struct nouveau_gpuobj *obj = NULL;
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int ret;
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ret = nouveau_gpuobj_new(dev, chan, 20, 16, NVOBJ_FLAG_ZERO_ALLOC |
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NVOBJ_FLAG_ZERO_FREE, &obj);
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if (ret)
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return ret;
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obj->engine = 2;
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obj->class = class;
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nv_wo32(obj, 0x00, class);
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ret = nouveau_ramht_insert(chan, handle, obj);
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nouveau_gpuobj_ref(NULL, &obj);
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return ret;
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}
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static int
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nv40_mpeg_init(struct drm_device *dev, int engine)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nv40_mpeg_engine *pmpeg = nv_engine(dev, engine);
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int i;
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/* VPE init */
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nv_mask(dev, 0x000200, 0x00000002, 0x00000000);
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nv_mask(dev, 0x000200, 0x00000002, 0x00000002);
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nv_wr32(dev, 0x00b0e0, 0x00000020); /* nvidia: rd 0x01, wr 0x20 */
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nv_wr32(dev, 0x00b0e8, 0x00000020); /* nvidia: rd 0x01, wr 0x20 */
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for (i = 0; i < dev_priv->engine.fb.num_tiles; i++)
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pmpeg->base.set_tile_region(dev, i);
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/* PMPEG init */
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nv_wr32(dev, 0x00b32c, 0x00000000);
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nv_wr32(dev, 0x00b314, 0x00000100);
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nv_wr32(dev, 0x00b220, 0x00000044);
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nv_wr32(dev, 0x00b300, 0x02001ec1);
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nv_mask(dev, 0x00b32c, 0x00000001, 0x00000001);
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nv_wr32(dev, 0x00b100, 0xffffffff);
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nv_wr32(dev, 0x00b140, 0xffffffff);
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if (!nv_wait(dev, 0x00b200, 0x00000001, 0x00000000)) {
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NV_ERROR(dev, "PMPEG init: 0x%08x\n", nv_rd32(dev, 0x00b200));
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return -EBUSY;
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}
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return 0;
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}
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static int
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nv40_mpeg_fini(struct drm_device *dev, int engine, bool suspend)
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{
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/*XXX: context save? */
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nv_mask(dev, 0x00b32c, 0x00000001, 0x00000000);
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nv_wr32(dev, 0x00b140, 0x00000000);
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return 0;
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}
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static int
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nv40_mpeg_mthd_dma(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data)
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{
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struct drm_device *dev = chan->dev;
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u32 inst = data << 4;
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u32 dma0 = nv_ri32(dev, inst + 0);
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u32 dma1 = nv_ri32(dev, inst + 4);
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u32 dma2 = nv_ri32(dev, inst + 8);
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u32 base = (dma2 & 0xfffff000) | (dma0 >> 20);
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u32 size = dma1 + 1;
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/* only allow linear DMA objects */
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if (!(dma0 & 0x00002000))
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return -EINVAL;
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if (mthd == 0x0190) {
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/* DMA_CMD */
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nv_mask(dev, 0x00b300, 0x00030000, (dma0 & 0x00030000));
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nv_wr32(dev, 0x00b334, base);
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nv_wr32(dev, 0x00b324, size);
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} else
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if (mthd == 0x01a0) {
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/* DMA_DATA */
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nv_mask(dev, 0x00b300, 0x000c0000, (dma0 & 0x00030000) << 2);
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nv_wr32(dev, 0x00b360, base);
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nv_wr32(dev, 0x00b364, size);
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} else {
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/* DMA_IMAGE, VRAM only */
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if (dma0 & 0x000c0000)
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return -EINVAL;
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nv_wr32(dev, 0x00b370, base);
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nv_wr32(dev, 0x00b374, size);
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}
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return 0;
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}
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static int
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nv40_mpeg_isr_chid(struct drm_device *dev, u32 inst)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpuobj *ctx;
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unsigned long flags;
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int i;
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spin_lock_irqsave(&dev_priv->channels.lock, flags);
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for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
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if (!dev_priv->channels.ptr[i])
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continue;
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ctx = dev_priv->channels.ptr[i]->engctx[NVOBJ_ENGINE_MPEG];
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if (ctx && ctx->pinst == inst)
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break;
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}
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spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
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return i;
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}
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static void
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nv40_vpe_set_tile_region(struct drm_device *dev, int i)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
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nv_wr32(dev, 0x00b008 + (i * 0x10), tile->pitch);
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nv_wr32(dev, 0x00b004 + (i * 0x10), tile->limit);
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nv_wr32(dev, 0x00b000 + (i * 0x10), tile->addr);
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}
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static void
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nv40_mpeg_isr(struct drm_device *dev)
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{
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u32 inst = (nv_rd32(dev, 0x00b318) & 0x000fffff) << 4;
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u32 chid = nv40_mpeg_isr_chid(dev, inst);
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u32 stat = nv_rd32(dev, 0x00b100);
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u32 type = nv_rd32(dev, 0x00b230);
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u32 mthd = nv_rd32(dev, 0x00b234);
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u32 data = nv_rd32(dev, 0x00b238);
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u32 show = stat;
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if (stat & 0x01000000) {
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/* happens on initial binding of the object */
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if (type == 0x00000020 && mthd == 0x0000) {
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nv_mask(dev, 0x00b308, 0x00000000, 0x00000000);
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show &= ~0x01000000;
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}
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if (type == 0x00000010) {
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if (!nouveau_gpuobj_mthd_call2(dev, chid, 0x3174, mthd, data))
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show &= ~0x01000000;
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}
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}
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nv_wr32(dev, 0x00b100, stat);
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nv_wr32(dev, 0x00b230, 0x00000001);
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if (show && nouveau_ratelimit()) {
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NV_INFO(dev, "PMPEG: Ch %d [0x%08x] 0x%08x 0x%08x 0x%08x 0x%08x\n",
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chid, inst, stat, type, mthd, data);
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}
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}
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static void
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nv40_vpe_isr(struct drm_device *dev)
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{
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if (nv_rd32(dev, 0x00b100))
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nv40_mpeg_isr(dev);
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if (nv_rd32(dev, 0x00b800)) {
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u32 stat = nv_rd32(dev, 0x00b800);
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NV_INFO(dev, "PMSRCH: 0x%08x\n", stat);
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nv_wr32(dev, 0xb800, stat);
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}
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}
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static void
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nv40_mpeg_destroy(struct drm_device *dev, int engine)
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{
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struct nv40_mpeg_engine *pmpeg = nv_engine(dev, engine);
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nouveau_irq_unregister(dev, 0);
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NVOBJ_ENGINE_DEL(dev, MPEG);
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kfree(pmpeg);
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}
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int
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nv40_mpeg_create(struct drm_device *dev)
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{
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struct nv40_mpeg_engine *pmpeg;
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pmpeg = kzalloc(sizeof(*pmpeg), GFP_KERNEL);
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if (!pmpeg)
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return -ENOMEM;
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pmpeg->base.destroy = nv40_mpeg_destroy;
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pmpeg->base.init = nv40_mpeg_init;
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pmpeg->base.fini = nv40_mpeg_fini;
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pmpeg->base.context_new = nv40_mpeg_context_new;
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pmpeg->base.context_del = nv40_mpeg_context_del;
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pmpeg->base.object_new = nv40_mpeg_object_new;
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/* ISR vector, PMC_ENABLE bit, and TILE regs are shared between
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* all VPE engines, for this driver's purposes the PMPEG engine
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* will be treated as the "master" and handle the global VPE
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* bits too
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*/
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pmpeg->base.set_tile_region = nv40_vpe_set_tile_region;
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nouveau_irq_register(dev, 0, nv40_vpe_isr);
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NVOBJ_ENGINE_ADD(dev, MPEG, &pmpeg->base);
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NVOBJ_CLASS(dev, 0x3174, MPEG);
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NVOBJ_MTHD (dev, 0x3174, 0x0190, nv40_mpeg_mthd_dma);
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NVOBJ_MTHD (dev, 0x3174, 0x01a0, nv40_mpeg_mthd_dma);
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NVOBJ_MTHD (dev, 0x3174, 0x01b0, nv40_mpeg_mthd_dma);
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#if 0
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NVOBJ_ENGINE_ADD(dev, ME, &pme->base);
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NVOBJ_CLASS(dev, 0x4075, ME);
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#endif
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return 0;
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}
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