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d7c9661115
This chip is no longer being actively developed for (it was superceded by the TILEPro64 in 2008), and in any case the existing compiler and toolchain in the community do not support it. It's unlikely that the kernel works with TILE64 at this point as the configuration has not been tested in years. The support is also awkward as it requires maintaining a significant number of ifdefs. So, just remove it altogether. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
378 lines
11 KiB
C
378 lines
11 KiB
C
/*
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* Copyright 2010 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*/
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#ifndef _ASM_TILE_PROCESSOR_H
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#define _ASM_TILE_PROCESSOR_H
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#include <arch/chip.h>
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#ifndef __ASSEMBLY__
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/*
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* NOTE: we don't include <linux/ptrace.h> or <linux/percpu.h> as one
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* normally would, due to #include dependencies.
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*/
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#include <linux/types.h>
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#include <asm/ptrace.h>
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#include <asm/percpu.h>
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#include <arch/spr_def.h>
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struct task_struct;
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struct thread_struct;
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typedef struct {
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unsigned long seg;
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} mm_segment_t;
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/*
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* Default implementation of macro that returns current
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* instruction pointer ("program counter").
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*/
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void *current_text_addr(void);
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#if CHIP_HAS_TILE_DMA()
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/* Capture the state of a suspended DMA. */
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struct tile_dma_state {
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int enabled;
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unsigned long src;
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unsigned long dest;
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unsigned long strides;
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unsigned long chunk_size;
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unsigned long src_chunk;
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unsigned long dest_chunk;
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unsigned long byte;
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unsigned long status;
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};
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/*
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* A mask of the DMA status register for selecting only the 'running'
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* and 'done' bits.
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*/
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#define DMA_STATUS_MASK \
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(SPR_DMA_STATUS__RUNNING_MASK | SPR_DMA_STATUS__DONE_MASK)
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#endif
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/*
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* Track asynchronous TLB events (faults and access violations)
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* that occur while we are in kernel mode from DMA or the SN processor.
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*/
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struct async_tlb {
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short fault_num; /* original fault number; 0 if none */
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char is_fault; /* was it a fault (vs an access violation) */
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char is_write; /* for fault: was it caused by a write? */
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unsigned long address; /* what address faulted? */
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};
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#ifdef CONFIG_HARDWALL
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struct hardwall_info;
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struct hardwall_task {
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/* Which hardwall is this task tied to? (or NULL if none) */
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struct hardwall_info *info;
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/* Chains this task into the list at info->task_head. */
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struct list_head list;
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};
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#ifdef __tilepro__
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#define HARDWALL_TYPES 1 /* udn */
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#else
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#define HARDWALL_TYPES 3 /* udn, idn, and ipi */
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#endif
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#endif
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struct thread_struct {
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/* kernel stack pointer */
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unsigned long ksp;
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/* kernel PC */
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unsigned long pc;
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/* starting user stack pointer (for page migration) */
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unsigned long usp0;
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/* pid of process that created this one */
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pid_t creator_pid;
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#if CHIP_HAS_TILE_DMA()
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/* DMA info for suspended threads (byte == 0 means no DMA state) */
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struct tile_dma_state tile_dma_state;
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#endif
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/* User EX_CONTEXT registers */
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unsigned long ex_context[2];
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/* User SYSTEM_SAVE registers */
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unsigned long system_save[4];
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/* User interrupt mask */
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unsigned long long interrupt_mask;
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/* User interrupt-control 0 state */
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unsigned long intctrl_0;
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/* Is this task currently doing a backtrace? */
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bool in_backtrace;
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/* Any other miscellaneous processor state bits */
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unsigned long proc_status;
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#if !CHIP_HAS_FIXED_INTVEC_BASE()
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/* Interrupt base for PL0 interrupts */
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unsigned long interrupt_vector_base;
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#endif
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/* Tile cache retry fifo high-water mark */
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unsigned long tile_rtf_hwm;
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#if CHIP_HAS_DSTREAM_PF()
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/* Data stream prefetch control */
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unsigned long dstream_pf;
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#endif
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#ifdef CONFIG_HARDWALL
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/* Hardwall information for various resources. */
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struct hardwall_task hardwall[HARDWALL_TYPES];
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#endif
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#if CHIP_HAS_TILE_DMA()
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/* Async DMA TLB fault information */
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struct async_tlb dma_async_tlb;
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#endif
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};
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#endif /* !__ASSEMBLY__ */
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/*
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* Start with "sp" this many bytes below the top of the kernel stack.
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* This allows us to be cache-aware when handling the initial save
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* of the pt_regs value to the stack.
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*/
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#define STACK_TOP_DELTA 64
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/*
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* When entering the kernel via a fault, start with the top of the
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* pt_regs structure this many bytes below the top of the page.
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* This aligns the pt_regs structure optimally for cache-line access.
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*/
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#ifdef __tilegx__
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#define KSTK_PTREGS_GAP 48
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#else
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#define KSTK_PTREGS_GAP 56
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#endif
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#ifndef __ASSEMBLY__
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#ifdef __tilegx__
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#define TASK_SIZE_MAX (_AC(1, UL) << (MAX_VA_WIDTH - 1))
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#else
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#define TASK_SIZE_MAX PAGE_OFFSET
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#endif
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/* TASK_SIZE and related variables are always checked in "current" context. */
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#ifdef CONFIG_COMPAT
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#define COMPAT_TASK_SIZE (1UL << 31)
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#define TASK_SIZE ((current_thread_info()->status & TS_COMPAT) ?\
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COMPAT_TASK_SIZE : TASK_SIZE_MAX)
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#else
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#define TASK_SIZE TASK_SIZE_MAX
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#endif
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#define VDSO_BASE ((unsigned long)current->active_mm->context.vdso_base)
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#define VDSO_SYM(x) (VDSO_BASE + (unsigned long)(x))
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#define STACK_TOP TASK_SIZE
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/* STACK_TOP_MAX is used temporarily in execve and should not check COMPAT. */
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#define STACK_TOP_MAX TASK_SIZE_MAX
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/*
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* This decides where the kernel will search for a free chunk of vm
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* space during mmap's, if it is using bottom-up mapping.
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*/
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#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
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#define HAVE_ARCH_PICK_MMAP_LAYOUT
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#define INIT_THREAD { \
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.ksp = (unsigned long)init_stack + THREAD_SIZE - STACK_TOP_DELTA, \
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.interrupt_mask = -1ULL \
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}
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/* Kernel stack top for the task that first boots on this cpu. */
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DECLARE_PER_CPU(unsigned long, boot_sp);
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/* PC to boot from on this cpu. */
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DECLARE_PER_CPU(unsigned long, boot_pc);
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/* Do necessary setup to start up a newly executed thread. */
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static inline void start_thread(struct pt_regs *regs,
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unsigned long pc, unsigned long usp)
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{
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regs->pc = pc;
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regs->sp = usp;
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single_step_execve();
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}
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/* Free all resources held by a thread. */
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static inline void release_thread(struct task_struct *dead_task)
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{
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/* Nothing for now */
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}
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extern int do_work_pending(struct pt_regs *regs, u32 flags);
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/*
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* Return saved (kernel) PC of a blocked thread.
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* Only used in a printk() in kernel/sched/core.c, so don't work too hard.
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*/
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#define thread_saved_pc(t) ((t)->thread.pc)
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unsigned long get_wchan(struct task_struct *p);
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/* Return initial ksp value for given task. */
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#define task_ksp0(task) \
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((unsigned long)(task)->stack + THREAD_SIZE - STACK_TOP_DELTA)
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/* Return some info about the user process TASK. */
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#define task_pt_regs(task) \
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((struct pt_regs *)(task_ksp0(task) - KSTK_PTREGS_GAP) - 1)
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#define current_pt_regs() \
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((struct pt_regs *)((stack_pointer | (THREAD_SIZE - 1)) - \
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STACK_TOP_DELTA - (KSTK_PTREGS_GAP - 1)) - 1)
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#define task_sp(task) (task_pt_regs(task)->sp)
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#define task_pc(task) (task_pt_regs(task)->pc)
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/* Aliases for pc and sp (used in fs/proc/array.c) */
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#define KSTK_EIP(task) task_pc(task)
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#define KSTK_ESP(task) task_sp(task)
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/* Fine-grained unaligned JIT support */
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#define GET_UNALIGN_CTL(tsk, adr) get_unalign_ctl((tsk), (adr))
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#define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val))
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extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr);
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extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);
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/* Standard format for printing registers and other word-size data. */
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#ifdef __tilegx__
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# define REGFMT "0x%016lx"
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#else
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# define REGFMT "0x%08lx"
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#endif
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/*
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* Do some slow action (e.g. read a slow SPR).
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* Note that this must also have compiler-barrier semantics since
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* it may be used in a busy loop reading memory.
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*/
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static inline void cpu_relax(void)
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{
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__insn_mfspr(SPR_PASS);
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barrier();
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}
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/* Info on this processor (see fs/proc/cpuinfo.c) */
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struct seq_operations;
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extern const struct seq_operations cpuinfo_op;
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/* Provide information about the chip model. */
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extern char chip_model[64];
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/* Data on which physical memory controller corresponds to which NUMA node. */
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extern int node_controller[];
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/* Does the heap allocator return hash-for-home pages by default? */
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extern int hash_default;
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/* Should kernel stack pages be hash-for-home? */
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extern int kstack_hash;
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/* Does MAP_ANONYMOUS return hash-for-home pages by default? */
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#define uheap_hash hash_default
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/* Are we using huge pages in the TLB for kernel data? */
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extern int kdata_huge;
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/* Support standard Linux prefetching. */
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#define ARCH_HAS_PREFETCH
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#define prefetch(x) __builtin_prefetch(x)
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#define PREFETCH_STRIDE CHIP_L2_LINE_SIZE()
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/* Bring a value into the L1D, faulting the TLB if necessary. */
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#ifdef __tilegx__
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#define prefetch_L1(x) __insn_prefetch_l1_fault((void *)(x))
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#else
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#define prefetch_L1(x) __insn_prefetch_L1((void *)(x))
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#endif
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#else /* __ASSEMBLY__ */
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/* Do some slow action (e.g. read a slow SPR). */
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#define CPU_RELAX mfspr zero, SPR_PASS
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#endif /* !__ASSEMBLY__ */
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/* Assembly code assumes that the PL is in the low bits. */
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#if SPR_EX_CONTEXT_1_1__PL_SHIFT != 0
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# error Fix assembly assumptions about PL
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#endif
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/* We sometimes use these macros for EX_CONTEXT_0_1 as well. */
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#if SPR_EX_CONTEXT_1_1__PL_SHIFT != SPR_EX_CONTEXT_0_1__PL_SHIFT || \
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SPR_EX_CONTEXT_1_1__PL_RMASK != SPR_EX_CONTEXT_0_1__PL_RMASK || \
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SPR_EX_CONTEXT_1_1__ICS_SHIFT != SPR_EX_CONTEXT_0_1__ICS_SHIFT || \
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SPR_EX_CONTEXT_1_1__ICS_RMASK != SPR_EX_CONTEXT_0_1__ICS_RMASK
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# error Fix assumptions that EX1 macros work for both PL0 and PL1
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#endif
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/* Allow pulling apart and recombining the PL and ICS bits in EX_CONTEXT. */
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#define EX1_PL(ex1) \
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(((ex1) >> SPR_EX_CONTEXT_1_1__PL_SHIFT) & SPR_EX_CONTEXT_1_1__PL_RMASK)
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#define EX1_ICS(ex1) \
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(((ex1) >> SPR_EX_CONTEXT_1_1__ICS_SHIFT) & SPR_EX_CONTEXT_1_1__ICS_RMASK)
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#define PL_ICS_EX1(pl, ics) \
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(((pl) << SPR_EX_CONTEXT_1_1__PL_SHIFT) | \
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((ics) << SPR_EX_CONTEXT_1_1__ICS_SHIFT))
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/*
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* Provide symbolic constants for PLs.
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*/
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#define USER_PL 0
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#if CONFIG_KERNEL_PL == 2
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#define GUEST_PL 1
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#endif
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#define KERNEL_PL CONFIG_KERNEL_PL
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/* SYSTEM_SAVE_K_0 holds the current cpu number ORed with ksp0. */
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#ifdef __tilegx__
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#define CPU_SHIFT 48
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#if CHIP_VA_WIDTH() > CPU_SHIFT
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# error Too many VA bits!
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#endif
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#define MAX_CPU_ID ((1 << (64 - CPU_SHIFT)) - 1)
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#define raw_smp_processor_id() \
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((int)(__insn_mfspr(SPR_SYSTEM_SAVE_K_0) >> CPU_SHIFT))
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#define get_current_ksp0() \
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((unsigned long)(((long)__insn_mfspr(SPR_SYSTEM_SAVE_K_0) << \
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(64 - CPU_SHIFT)) >> (64 - CPU_SHIFT)))
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#define next_current_ksp0(task) ({ \
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unsigned long __ksp0 = task_ksp0(task) & ((1UL << CPU_SHIFT) - 1); \
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unsigned long __cpu = (long)raw_smp_processor_id() << CPU_SHIFT; \
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__ksp0 | __cpu; \
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})
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#else
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#define LOG2_NR_CPU_IDS 6
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#define MAX_CPU_ID ((1 << LOG2_NR_CPU_IDS) - 1)
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#define raw_smp_processor_id() \
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((int)__insn_mfspr(SPR_SYSTEM_SAVE_K_0) & MAX_CPU_ID)
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#define get_current_ksp0() \
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(__insn_mfspr(SPR_SYSTEM_SAVE_K_0) & ~MAX_CPU_ID)
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#define next_current_ksp0(task) ({ \
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unsigned long __ksp0 = task_ksp0(task); \
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int __cpu = raw_smp_processor_id(); \
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BUG_ON(__ksp0 & MAX_CPU_ID); \
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__ksp0 | __cpu; \
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})
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#endif
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#if CONFIG_NR_CPUS > (MAX_CPU_ID + 1)
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# error Too many cpus!
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#endif
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#endif /* _ASM_TILE_PROCESSOR_H */
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