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9f403603f2
This changes the meaning of what we reported as "core" clock previously. The shader/rop units are allegedly supposed to be run at the base clock listed in the perf table, while the geometric clock can be bumped from this value on some boards. So that we can report both, we'll report the base clock as "shader" (since the shaders *do* run at it), and the geometric clock as "core". Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
369 lines
9.6 KiB
C
369 lines
9.6 KiB
C
/*
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* Copyright 2010 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "drmP.h"
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#include "nouveau_drv.h"
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#include "nouveau_pm.h"
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static void
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legacy_perf_init(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nvbios *bios = &dev_priv->vbios;
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struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
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char *perf, *entry, *bmp = &bios->data[bios->offset];
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int headerlen, use_straps;
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if (bmp[5] < 0x5 || bmp[6] < 0x14) {
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NV_DEBUG(dev, "BMP version too old for perf\n");
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return;
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}
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perf = ROMPTR(bios, bmp[0x73]);
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if (!perf) {
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NV_DEBUG(dev, "No memclock table pointer found.\n");
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return;
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}
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switch (perf[0]) {
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case 0x12:
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case 0x14:
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case 0x18:
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use_straps = 0;
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headerlen = 1;
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break;
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case 0x01:
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use_straps = perf[1] & 1;
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headerlen = (use_straps ? 8 : 2);
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break;
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default:
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NV_WARN(dev, "Unknown memclock table version %x.\n", perf[0]);
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return;
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}
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entry = perf + headerlen;
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if (use_straps)
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entry += (nv_rd32(dev, NV_PEXTDEV_BOOT_0) & 0x3c) >> 1;
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sprintf(pm->perflvl[0].name, "performance_level_0");
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pm->perflvl[0].memory = ROM16(entry[0]) * 20;
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pm->nr_perflvl = 1;
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}
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static struct nouveau_pm_memtiming *
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nouveau_perf_timing(struct drm_device *dev, struct bit_entry *P,
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u16 memclk, u8 *entry, u8 recordlen, u8 entries)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
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struct nvbios *bios = &dev_priv->vbios;
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u8 ramcfg;
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int i;
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/* perf v2 has a separate "timing map" table, we have to match
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* the target memory clock to a specific entry, *then* use
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* ramcfg to select the correct subentry
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*/
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if (P->version == 2) {
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u8 *tmap = ROMPTR(bios, P->data[4]);
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if (!tmap) {
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NV_DEBUG(dev, "no timing map pointer\n");
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return NULL;
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}
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if (tmap[0] != 0x10) {
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NV_WARN(dev, "timing map 0x%02x unknown\n", tmap[0]);
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return NULL;
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}
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entry = tmap + tmap[1];
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recordlen = tmap[2] + (tmap[4] * tmap[3]);
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for (i = 0; i < tmap[5]; i++, entry += recordlen) {
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if (memclk >= ROM16(entry[0]) &&
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memclk <= ROM16(entry[2]))
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break;
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}
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if (i == tmap[5]) {
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NV_WARN(dev, "no match in timing map table\n");
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return NULL;
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}
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entry += tmap[2];
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recordlen = tmap[3];
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entries = tmap[4];
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}
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ramcfg = (nv_rd32(dev, NV_PEXTDEV_BOOT_0) & 0x0000003c) >> 2;
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if (bios->ram_restrict_tbl_ptr)
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ramcfg = bios->data[bios->ram_restrict_tbl_ptr + ramcfg];
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if (ramcfg >= entries) {
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NV_WARN(dev, "ramcfg strap out of bounds!\n");
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return NULL;
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}
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entry += ramcfg * recordlen;
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if (entry[1] >= pm->memtimings.nr_timing) {
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if (entry[1] != 0xff)
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NV_WARN(dev, "timingset %d does not exist\n", entry[1]);
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return NULL;
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}
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return &pm->memtimings.timing[entry[1]];
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}
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static void
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nouveau_perf_voltage(struct drm_device *dev, struct bit_entry *P,
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struct nouveau_pm_level *perflvl)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nvbios *bios = &dev_priv->vbios;
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u8 *vmap;
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int id;
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id = perflvl->volt_min;
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perflvl->volt_min = 0;
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/* boards using voltage table version <0x40 store the voltage
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* level directly in the perflvl entry as a multiple of 10mV
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*/
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if (dev_priv->engine.pm.voltage.version < 0x40) {
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perflvl->volt_min = id * 10000;
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perflvl->volt_max = perflvl->volt_min;
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return;
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}
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/* on newer ones, the perflvl stores an index into yet another
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* vbios table containing a min/max voltage value for the perflvl
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*/
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if (P->version != 2 || P->length < 34) {
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NV_DEBUG(dev, "where's our volt map table ptr? %d %d\n",
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P->version, P->length);
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return;
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}
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vmap = ROMPTR(bios, P->data[32]);
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if (!vmap) {
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NV_DEBUG(dev, "volt map table pointer invalid\n");
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return;
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}
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if (id < vmap[3]) {
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vmap += vmap[1] + (vmap[2] * id);
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perflvl->volt_min = ROM32(vmap[0]);
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perflvl->volt_max = ROM32(vmap[4]);
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}
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}
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void
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nouveau_perf_init(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
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struct nvbios *bios = &dev_priv->vbios;
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struct bit_entry P;
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struct nouveau_pm_memtimings *memtimings = &pm->memtimings;
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struct nouveau_pm_tbl_header mt_hdr;
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u8 version, headerlen, recordlen, entries;
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u8 *perf, *entry;
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int vid, i;
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if (bios->type == NVBIOS_BIT) {
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if (bit_table(dev, 'P', &P))
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return;
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if (P.version != 1 && P.version != 2) {
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NV_WARN(dev, "unknown perf for BIT P %d\n", P.version);
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return;
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}
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perf = ROMPTR(bios, P.data[0]);
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version = perf[0];
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headerlen = perf[1];
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if (version < 0x40) {
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recordlen = perf[3] + (perf[4] * perf[5]);
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entries = perf[2];
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} else {
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recordlen = perf[2] + (perf[3] * perf[4]);
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entries = perf[5];
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}
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} else {
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if (bios->data[bios->offset + 6] < 0x25) {
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legacy_perf_init(dev);
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return;
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}
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perf = ROMPTR(bios, bios->data[bios->offset + 0x94]);
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if (!perf) {
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NV_DEBUG(dev, "perf table pointer invalid\n");
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return;
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}
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version = perf[1];
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headerlen = perf[0];
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recordlen = perf[3];
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entries = perf[2];
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}
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if (entries > NOUVEAU_PM_MAX_LEVEL) {
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NV_DEBUG(dev, "perf table has too many entries - buggy vbios?\n");
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entries = NOUVEAU_PM_MAX_LEVEL;
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}
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entry = perf + headerlen;
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/* For version 0x15, initialize memtiming table */
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if(version == 0x15) {
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memtimings->timing =
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kcalloc(entries, sizeof(*memtimings->timing), GFP_KERNEL);
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if(!memtimings) {
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NV_WARN(dev,"Could not allocate memtiming table\n");
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return;
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}
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mt_hdr.entry_cnt = entries;
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mt_hdr.entry_len = 14;
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mt_hdr.version = version;
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mt_hdr.header_len = 4;
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}
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for (i = 0; i < entries; i++) {
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struct nouveau_pm_level *perflvl = &pm->perflvl[pm->nr_perflvl];
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perflvl->timing = NULL;
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if (entry[0] == 0xff) {
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entry += recordlen;
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continue;
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}
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switch (version) {
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case 0x12:
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case 0x13:
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case 0x15:
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perflvl->fanspeed = entry[55];
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if (recordlen > 56)
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perflvl->volt_min = entry[56];
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perflvl->core = ROM32(entry[1]) * 10;
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perflvl->memory = ROM32(entry[5]) * 20;
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break;
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case 0x21:
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case 0x23:
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case 0x24:
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perflvl->fanspeed = entry[4];
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perflvl->volt_min = entry[5];
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perflvl->shader = ROM16(entry[6]) * 1000;
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perflvl->core = perflvl->shader;
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perflvl->core += (signed char)entry[8] * 1000;
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if (dev_priv->chipset == 0x49 ||
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dev_priv->chipset == 0x4b)
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perflvl->memory = ROM16(entry[11]) * 1000;
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else
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perflvl->memory = ROM16(entry[11]) * 2000;
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break;
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case 0x25:
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perflvl->fanspeed = entry[4];
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perflvl->volt_min = entry[5];
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perflvl->core = ROM16(entry[6]) * 1000;
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perflvl->shader = ROM16(entry[10]) * 1000;
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perflvl->memory = ROM16(entry[12]) * 1000;
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break;
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case 0x30:
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perflvl->memscript = ROM16(entry[2]);
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case 0x35:
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perflvl->fanspeed = entry[6];
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perflvl->volt_min = entry[7];
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perflvl->core = ROM16(entry[8]) * 1000;
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perflvl->shader = ROM16(entry[10]) * 1000;
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perflvl->memory = ROM16(entry[12]) * 1000;
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/*XXX: confirm on 0x35 */
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perflvl->unk05 = ROM16(entry[16]) * 1000;
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break;
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case 0x40:
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#define subent(n) (ROM16(entry[perf[2] + ((n) * perf[3])]) & 0xfff) * 1000
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perflvl->fanspeed = 0; /*XXX*/
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perflvl->volt_min = entry[2];
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if (dev_priv->card_type == NV_50) {
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perflvl->core = subent(0);
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perflvl->shader = subent(1);
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perflvl->memory = subent(2);
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perflvl->vdec = subent(3);
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perflvl->unka0 = subent(4);
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} else {
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perflvl->hub06 = subent(0);
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perflvl->hub01 = subent(1);
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perflvl->copy = subent(2);
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perflvl->shader = subent(3);
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perflvl->rop = subent(4);
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perflvl->memory = subent(5);
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perflvl->vdec = subent(6);
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perflvl->daemon = subent(10);
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perflvl->hub07 = subent(11);
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perflvl->core = perflvl->shader / 2;
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}
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break;
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}
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/* make sure vid is valid */
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nouveau_perf_voltage(dev, &P, perflvl);
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if (pm->voltage.supported && perflvl->volt_min) {
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vid = nouveau_volt_vid_lookup(dev, perflvl->volt_min);
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if (vid < 0) {
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NV_DEBUG(dev, "drop perflvl %d, bad vid\n", i);
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entry += recordlen;
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continue;
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}
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}
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/* get the corresponding memory timings */
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if (version == 0x15) {
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memtimings->timing[i].id = i;
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nv30_mem_timing_entry(dev,&mt_hdr,(struct nouveau_pm_tbl_entry*) &entry[41],0,&memtimings->timing[i]);
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perflvl->timing = &memtimings->timing[i];
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} else if (version > 0x15) {
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/* last 3 args are for < 0x40, ignored for >= 0x40 */
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perflvl->timing =
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nouveau_perf_timing(dev, &P,
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perflvl->memory / 1000,
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entry + perf[3],
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perf[5], perf[4]);
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}
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snprintf(perflvl->name, sizeof(perflvl->name),
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"performance_level_%d", i);
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perflvl->id = i;
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pm->nr_perflvl++;
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entry += recordlen;
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}
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}
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void
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nouveau_perf_fini(struct drm_device *dev)
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{
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}
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