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96a388de5d
Move the headers to include/asm-x86 and fixup the header install make rules Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
189 lines
6.2 KiB
C
189 lines
6.2 KiB
C
/******************************************************************************
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* arch-x86_32.h
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*
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* Guest OS interface to x86 32-bit Xen.
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*
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* Copyright (c) 2004, K A Fraser
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*/
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#ifndef __XEN_PUBLIC_ARCH_X86_32_H__
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#define __XEN_PUBLIC_ARCH_X86_32_H__
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#ifdef __XEN__
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#define __DEFINE_GUEST_HANDLE(name, type) \
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typedef struct { type *p; } __guest_handle_ ## name
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#else
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#define __DEFINE_GUEST_HANDLE(name, type) \
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typedef type * __guest_handle_ ## name
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#endif
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#define DEFINE_GUEST_HANDLE_STRUCT(name) \
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__DEFINE_GUEST_HANDLE(name, struct name)
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#define DEFINE_GUEST_HANDLE(name) __DEFINE_GUEST_HANDLE(name, name)
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#define GUEST_HANDLE(name) __guest_handle_ ## name
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#ifndef __ASSEMBLY__
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/* Guest handles for primitive C types. */
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__DEFINE_GUEST_HANDLE(uchar, unsigned char);
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__DEFINE_GUEST_HANDLE(uint, unsigned int);
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__DEFINE_GUEST_HANDLE(ulong, unsigned long);
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DEFINE_GUEST_HANDLE(char);
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DEFINE_GUEST_HANDLE(int);
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DEFINE_GUEST_HANDLE(long);
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DEFINE_GUEST_HANDLE(void);
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#endif
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/*
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* SEGMENT DESCRIPTOR TABLES
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*/
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/*
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* A number of GDT entries are reserved by Xen. These are not situated at the
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* start of the GDT because some stupid OSes export hard-coded selector values
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* in their ABI. These hard-coded values are always near the start of the GDT,
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* so Xen places itself out of the way, at the far end of the GDT.
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*/
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#define FIRST_RESERVED_GDT_PAGE 14
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#define FIRST_RESERVED_GDT_BYTE (FIRST_RESERVED_GDT_PAGE * 4096)
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#define FIRST_RESERVED_GDT_ENTRY (FIRST_RESERVED_GDT_BYTE / 8)
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/*
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* These flat segments are in the Xen-private section of every GDT. Since these
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* are also present in the initial GDT, many OSes will be able to avoid
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* installing their own GDT.
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*/
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#define FLAT_RING1_CS 0xe019 /* GDT index 259 */
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#define FLAT_RING1_DS 0xe021 /* GDT index 260 */
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#define FLAT_RING1_SS 0xe021 /* GDT index 260 */
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#define FLAT_RING3_CS 0xe02b /* GDT index 261 */
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#define FLAT_RING3_DS 0xe033 /* GDT index 262 */
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#define FLAT_RING3_SS 0xe033 /* GDT index 262 */
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#define FLAT_KERNEL_CS FLAT_RING1_CS
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#define FLAT_KERNEL_DS FLAT_RING1_DS
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#define FLAT_KERNEL_SS FLAT_RING1_SS
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#define FLAT_USER_CS FLAT_RING3_CS
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#define FLAT_USER_DS FLAT_RING3_DS
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#define FLAT_USER_SS FLAT_RING3_SS
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/* And the trap vector is... */
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#define TRAP_INSTR "int $0x82"
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/*
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* Virtual addresses beyond this are not modifiable by guest OSes. The
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* machine->physical mapping table starts at this address, read-only.
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*/
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#ifdef CONFIG_X86_PAE
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#define __HYPERVISOR_VIRT_START 0xF5800000
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#else
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#define __HYPERVISOR_VIRT_START 0xFC000000
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#endif
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#ifndef HYPERVISOR_VIRT_START
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#define HYPERVISOR_VIRT_START mk_unsigned_long(__HYPERVISOR_VIRT_START)
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#endif
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#ifndef machine_to_phys_mapping
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#define machine_to_phys_mapping ((unsigned long *)HYPERVISOR_VIRT_START)
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#endif
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/* Maximum number of virtual CPUs in multi-processor guests. */
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#define MAX_VIRT_CPUS 32
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#ifndef __ASSEMBLY__
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/*
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* Send an array of these to HYPERVISOR_set_trap_table()
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*/
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#define TI_GET_DPL(_ti) ((_ti)->flags & 3)
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#define TI_GET_IF(_ti) ((_ti)->flags & 4)
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#define TI_SET_DPL(_ti, _dpl) ((_ti)->flags |= (_dpl))
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#define TI_SET_IF(_ti, _if) ((_ti)->flags |= ((!!(_if))<<2))
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struct trap_info {
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uint8_t vector; /* exception vector */
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uint8_t flags; /* 0-3: privilege level; 4: clear event enable? */
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uint16_t cs; /* code selector */
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unsigned long address; /* code offset */
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};
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DEFINE_GUEST_HANDLE_STRUCT(trap_info);
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struct cpu_user_regs {
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uint32_t ebx;
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uint32_t ecx;
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uint32_t edx;
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uint32_t esi;
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uint32_t edi;
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uint32_t ebp;
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uint32_t eax;
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uint16_t error_code; /* private */
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uint16_t entry_vector; /* private */
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uint32_t eip;
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uint16_t cs;
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uint8_t saved_upcall_mask;
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uint8_t _pad0;
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uint32_t eflags; /* eflags.IF == !saved_upcall_mask */
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uint32_t esp;
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uint16_t ss, _pad1;
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uint16_t es, _pad2;
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uint16_t ds, _pad3;
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uint16_t fs, _pad4;
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uint16_t gs, _pad5;
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};
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DEFINE_GUEST_HANDLE_STRUCT(cpu_user_regs);
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typedef uint64_t tsc_timestamp_t; /* RDTSC timestamp */
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/*
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* The following is all CPU context. Note that the fpu_ctxt block is filled
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* in by FXSAVE if the CPU has feature FXSR; otherwise FSAVE is used.
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*/
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struct vcpu_guest_context {
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/* FPU registers come first so they can be aligned for FXSAVE/FXRSTOR. */
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struct { char x[512]; } fpu_ctxt; /* User-level FPU registers */
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#define VGCF_I387_VALID (1<<0)
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#define VGCF_HVM_GUEST (1<<1)
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#define VGCF_IN_KERNEL (1<<2)
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unsigned long flags; /* VGCF_* flags */
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struct cpu_user_regs user_regs; /* User-level CPU registers */
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struct trap_info trap_ctxt[256]; /* Virtual IDT */
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unsigned long ldt_base, ldt_ents; /* LDT (linear address, # ents) */
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unsigned long gdt_frames[16], gdt_ents; /* GDT (machine frames, # ents) */
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unsigned long kernel_ss, kernel_sp; /* Virtual TSS (only SS1/SP1) */
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unsigned long ctrlreg[8]; /* CR0-CR7 (control registers) */
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unsigned long debugreg[8]; /* DB0-DB7 (debug registers) */
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unsigned long event_callback_cs; /* CS:EIP of event callback */
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unsigned long event_callback_eip;
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unsigned long failsafe_callback_cs; /* CS:EIP of failsafe callback */
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unsigned long failsafe_callback_eip;
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unsigned long vm_assist; /* VMASST_TYPE_* bitmap */
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};
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DEFINE_GUEST_HANDLE_STRUCT(vcpu_guest_context);
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struct arch_shared_info {
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unsigned long max_pfn; /* max pfn that appears in table */
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/* Frame containing list of mfns containing list of mfns containing p2m. */
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unsigned long pfn_to_mfn_frame_list_list;
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unsigned long nmi_reason;
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};
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struct arch_vcpu_info {
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unsigned long cr2;
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unsigned long pad[5]; /* sizeof(struct vcpu_info) == 64 */
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};
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#endif /* !__ASSEMBLY__ */
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/*
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* Prefix forces emulation of some non-trapping instructions.
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* Currently only CPUID.
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*/
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#ifdef __ASSEMBLY__
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#define XEN_EMULATE_PREFIX .byte 0x0f,0x0b,0x78,0x65,0x6e ;
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#define XEN_CPUID XEN_EMULATE_PREFIX cpuid
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#else
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#define XEN_EMULATE_PREFIX ".byte 0x0f,0x0b,0x78,0x65,0x6e ; "
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#define XEN_CPUID XEN_EMULATE_PREFIX "cpuid"
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#endif
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#endif
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