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304989fe59
Signed-off-by: Bruce Allan <bruce.w.allan@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
306 lines
10 KiB
C
306 lines
10 KiB
C
/*
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This file is provided under a dual BSD/GPLv2 license. When using or
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redistributing this file, you may do so under either license.
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GPL LICENSE SUMMARY
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Copyright(c) 2014 Intel Corporation.
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This program is free software; you can redistribute it and/or modify
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it under the terms of version 2 of the GNU General Public License as
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published by the Free Software Foundation.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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Contact Information:
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qat-linux@intel.com
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BSD LICENSE
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Copyright(c) 2014 Intel Corporation.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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* Neither the name of Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ICP_QAT_HW_H_
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#define _ICP_QAT_HW_H_
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enum icp_qat_hw_ae_id {
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ICP_QAT_HW_AE_0 = 0,
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ICP_QAT_HW_AE_1 = 1,
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ICP_QAT_HW_AE_2 = 2,
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ICP_QAT_HW_AE_3 = 3,
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ICP_QAT_HW_AE_4 = 4,
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ICP_QAT_HW_AE_5 = 5,
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ICP_QAT_HW_AE_6 = 6,
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ICP_QAT_HW_AE_7 = 7,
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ICP_QAT_HW_AE_8 = 8,
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ICP_QAT_HW_AE_9 = 9,
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ICP_QAT_HW_AE_10 = 10,
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ICP_QAT_HW_AE_11 = 11,
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ICP_QAT_HW_AE_DELIMITER = 12
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};
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enum icp_qat_hw_qat_id {
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ICP_QAT_HW_QAT_0 = 0,
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ICP_QAT_HW_QAT_1 = 1,
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ICP_QAT_HW_QAT_2 = 2,
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ICP_QAT_HW_QAT_3 = 3,
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ICP_QAT_HW_QAT_4 = 4,
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ICP_QAT_HW_QAT_5 = 5,
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ICP_QAT_HW_QAT_DELIMITER = 6
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};
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enum icp_qat_hw_auth_algo {
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ICP_QAT_HW_AUTH_ALGO_NULL = 0,
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ICP_QAT_HW_AUTH_ALGO_SHA1 = 1,
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ICP_QAT_HW_AUTH_ALGO_MD5 = 2,
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ICP_QAT_HW_AUTH_ALGO_SHA224 = 3,
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ICP_QAT_HW_AUTH_ALGO_SHA256 = 4,
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ICP_QAT_HW_AUTH_ALGO_SHA384 = 5,
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ICP_QAT_HW_AUTH_ALGO_SHA512 = 6,
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ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC = 7,
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ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC = 8,
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ICP_QAT_HW_AUTH_ALGO_AES_F9 = 9,
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ICP_QAT_HW_AUTH_ALGO_GALOIS_128 = 10,
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ICP_QAT_HW_AUTH_ALGO_GALOIS_64 = 11,
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ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 = 12,
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ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 = 13,
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ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3 = 14,
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ICP_QAT_HW_AUTH_RESERVED_1 = 15,
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ICP_QAT_HW_AUTH_RESERVED_2 = 16,
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ICP_QAT_HW_AUTH_ALGO_SHA3_256 = 17,
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ICP_QAT_HW_AUTH_RESERVED_3 = 18,
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ICP_QAT_HW_AUTH_ALGO_SHA3_512 = 19,
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ICP_QAT_HW_AUTH_ALGO_DELIMITER = 20
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};
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enum icp_qat_hw_auth_mode {
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ICP_QAT_HW_AUTH_MODE0 = 0,
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ICP_QAT_HW_AUTH_MODE1 = 1,
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ICP_QAT_HW_AUTH_MODE2 = 2,
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ICP_QAT_HW_AUTH_MODE_DELIMITER = 3
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};
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struct icp_qat_hw_auth_config {
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uint32_t config;
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uint32_t reserved;
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};
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#define QAT_AUTH_MODE_BITPOS 4
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#define QAT_AUTH_MODE_MASK 0xF
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#define QAT_AUTH_ALGO_BITPOS 0
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#define QAT_AUTH_ALGO_MASK 0xF
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#define QAT_AUTH_CMP_BITPOS 8
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#define QAT_AUTH_CMP_MASK 0x7F
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#define QAT_AUTH_SHA3_PADDING_BITPOS 16
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#define QAT_AUTH_SHA3_PADDING_MASK 0x1
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#define QAT_AUTH_ALGO_SHA3_BITPOS 22
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#define QAT_AUTH_ALGO_SHA3_MASK 0x3
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#define ICP_QAT_HW_AUTH_CONFIG_BUILD(mode, algo, cmp_len) \
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(((mode & QAT_AUTH_MODE_MASK) << QAT_AUTH_MODE_BITPOS) | \
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((algo & QAT_AUTH_ALGO_MASK) << QAT_AUTH_ALGO_BITPOS) | \
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(((algo >> 4) & QAT_AUTH_ALGO_SHA3_MASK) << \
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QAT_AUTH_ALGO_SHA3_BITPOS) | \
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(((((algo == ICP_QAT_HW_AUTH_ALGO_SHA3_256) || \
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(algo == ICP_QAT_HW_AUTH_ALGO_SHA3_512)) ? 1 : 0) \
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& QAT_AUTH_SHA3_PADDING_MASK) << QAT_AUTH_SHA3_PADDING_BITPOS) | \
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((cmp_len & QAT_AUTH_CMP_MASK) << QAT_AUTH_CMP_BITPOS))
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struct icp_qat_hw_auth_counter {
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__be32 counter;
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uint32_t reserved;
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};
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#define QAT_AUTH_COUNT_MASK 0xFFFFFFFF
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#define QAT_AUTH_COUNT_BITPOS 0
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#define ICP_QAT_HW_AUTH_COUNT_BUILD(val) \
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(((val) & QAT_AUTH_COUNT_MASK) << QAT_AUTH_COUNT_BITPOS)
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struct icp_qat_hw_auth_setup {
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struct icp_qat_hw_auth_config auth_config;
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struct icp_qat_hw_auth_counter auth_counter;
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};
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#define QAT_HW_DEFAULT_ALIGNMENT 8
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#define QAT_HW_ROUND_UP(val, n) (((val) + ((n) - 1)) & (~(n - 1)))
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#define ICP_QAT_HW_NULL_STATE1_SZ 32
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#define ICP_QAT_HW_MD5_STATE1_SZ 16
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#define ICP_QAT_HW_SHA1_STATE1_SZ 20
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#define ICP_QAT_HW_SHA224_STATE1_SZ 32
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#define ICP_QAT_HW_SHA256_STATE1_SZ 32
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#define ICP_QAT_HW_SHA3_256_STATE1_SZ 32
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#define ICP_QAT_HW_SHA384_STATE1_SZ 64
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#define ICP_QAT_HW_SHA512_STATE1_SZ 64
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#define ICP_QAT_HW_SHA3_512_STATE1_SZ 64
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#define ICP_QAT_HW_SHA3_224_STATE1_SZ 28
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#define ICP_QAT_HW_SHA3_384_STATE1_SZ 48
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#define ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ 16
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#define ICP_QAT_HW_AES_CBC_MAC_STATE1_SZ 16
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#define ICP_QAT_HW_AES_F9_STATE1_SZ 32
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#define ICP_QAT_HW_KASUMI_F9_STATE1_SZ 16
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#define ICP_QAT_HW_GALOIS_128_STATE1_SZ 16
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#define ICP_QAT_HW_SNOW_3G_UIA2_STATE1_SZ 8
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#define ICP_QAT_HW_ZUC_3G_EIA3_STATE1_SZ 8
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#define ICP_QAT_HW_NULL_STATE2_SZ 32
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#define ICP_QAT_HW_MD5_STATE2_SZ 16
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#define ICP_QAT_HW_SHA1_STATE2_SZ 20
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#define ICP_QAT_HW_SHA224_STATE2_SZ 32
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#define ICP_QAT_HW_SHA256_STATE2_SZ 32
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#define ICP_QAT_HW_SHA3_256_STATE2_SZ 0
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#define ICP_QAT_HW_SHA384_STATE2_SZ 64
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#define ICP_QAT_HW_SHA512_STATE2_SZ 64
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#define ICP_QAT_HW_SHA3_512_STATE2_SZ 0
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#define ICP_QAT_HW_SHA3_224_STATE2_SZ 0
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#define ICP_QAT_HW_SHA3_384_STATE2_SZ 0
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#define ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ 16
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#define ICP_QAT_HW_AES_CBC_MAC_KEY_SZ 16
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#define ICP_QAT_HW_AES_CCM_CBC_E_CTR0_SZ 16
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#define ICP_QAT_HW_F9_IK_SZ 16
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#define ICP_QAT_HW_F9_FK_SZ 16
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#define ICP_QAT_HW_KASUMI_F9_STATE2_SZ (ICP_QAT_HW_F9_IK_SZ + \
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ICP_QAT_HW_F9_FK_SZ)
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#define ICP_QAT_HW_AES_F9_STATE2_SZ ICP_QAT_HW_KASUMI_F9_STATE2_SZ
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#define ICP_QAT_HW_SNOW_3G_UIA2_STATE2_SZ 24
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#define ICP_QAT_HW_ZUC_3G_EIA3_STATE2_SZ 32
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#define ICP_QAT_HW_GALOIS_H_SZ 16
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#define ICP_QAT_HW_GALOIS_LEN_A_SZ 8
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#define ICP_QAT_HW_GALOIS_E_CTR0_SZ 16
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struct icp_qat_hw_auth_sha512 {
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struct icp_qat_hw_auth_setup inner_setup;
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uint8_t state1[ICP_QAT_HW_SHA512_STATE1_SZ];
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struct icp_qat_hw_auth_setup outer_setup;
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uint8_t state2[ICP_QAT_HW_SHA512_STATE2_SZ];
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};
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struct icp_qat_hw_auth_algo_blk {
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struct icp_qat_hw_auth_sha512 sha;
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};
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#define ICP_QAT_HW_GALOIS_LEN_A_BITPOS 0
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#define ICP_QAT_HW_GALOIS_LEN_A_MASK 0xFFFFFFFF
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enum icp_qat_hw_cipher_algo {
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ICP_QAT_HW_CIPHER_ALGO_NULL = 0,
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ICP_QAT_HW_CIPHER_ALGO_DES = 1,
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ICP_QAT_HW_CIPHER_ALGO_3DES = 2,
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ICP_QAT_HW_CIPHER_ALGO_AES128 = 3,
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ICP_QAT_HW_CIPHER_ALGO_AES192 = 4,
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ICP_QAT_HW_CIPHER_ALGO_AES256 = 5,
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ICP_QAT_HW_CIPHER_ALGO_ARC4 = 6,
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ICP_QAT_HW_CIPHER_ALGO_KASUMI = 7,
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ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 = 8,
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ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3 = 9,
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ICP_QAT_HW_CIPHER_DELIMITER = 10
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};
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enum icp_qat_hw_cipher_mode {
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ICP_QAT_HW_CIPHER_ECB_MODE = 0,
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ICP_QAT_HW_CIPHER_CBC_MODE = 1,
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ICP_QAT_HW_CIPHER_CTR_MODE = 2,
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ICP_QAT_HW_CIPHER_F8_MODE = 3,
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ICP_QAT_HW_CIPHER_XTS_MODE = 6,
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ICP_QAT_HW_CIPHER_MODE_DELIMITER = 7
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};
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struct icp_qat_hw_cipher_config {
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uint32_t val;
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uint32_t reserved;
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};
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enum icp_qat_hw_cipher_dir {
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ICP_QAT_HW_CIPHER_ENCRYPT = 0,
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ICP_QAT_HW_CIPHER_DECRYPT = 1,
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};
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enum icp_qat_hw_cipher_convert {
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ICP_QAT_HW_CIPHER_NO_CONVERT = 0,
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ICP_QAT_HW_CIPHER_KEY_CONVERT = 1,
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};
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#define QAT_CIPHER_MODE_BITPOS 4
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#define QAT_CIPHER_MODE_MASK 0xF
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#define QAT_CIPHER_ALGO_BITPOS 0
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#define QAT_CIPHER_ALGO_MASK 0xF
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#define QAT_CIPHER_CONVERT_BITPOS 9
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#define QAT_CIPHER_CONVERT_MASK 0x1
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#define QAT_CIPHER_DIR_BITPOS 8
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#define QAT_CIPHER_DIR_MASK 0x1
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#define QAT_CIPHER_MODE_F8_KEY_SZ_MULT 2
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#define QAT_CIPHER_MODE_XTS_KEY_SZ_MULT 2
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#define ICP_QAT_HW_CIPHER_CONFIG_BUILD(mode, algo, convert, dir) \
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(((mode & QAT_CIPHER_MODE_MASK) << QAT_CIPHER_MODE_BITPOS) | \
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((algo & QAT_CIPHER_ALGO_MASK) << QAT_CIPHER_ALGO_BITPOS) | \
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((convert & QAT_CIPHER_CONVERT_MASK) << QAT_CIPHER_CONVERT_BITPOS) | \
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((dir & QAT_CIPHER_DIR_MASK) << QAT_CIPHER_DIR_BITPOS))
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#define ICP_QAT_HW_DES_BLK_SZ 8
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#define ICP_QAT_HW_3DES_BLK_SZ 8
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#define ICP_QAT_HW_NULL_BLK_SZ 8
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#define ICP_QAT_HW_AES_BLK_SZ 16
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#define ICP_QAT_HW_KASUMI_BLK_SZ 8
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#define ICP_QAT_HW_SNOW_3G_BLK_SZ 8
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#define ICP_QAT_HW_ZUC_3G_BLK_SZ 8
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#define ICP_QAT_HW_NULL_KEY_SZ 256
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#define ICP_QAT_HW_DES_KEY_SZ 8
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#define ICP_QAT_HW_3DES_KEY_SZ 24
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#define ICP_QAT_HW_AES_128_KEY_SZ 16
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#define ICP_QAT_HW_AES_192_KEY_SZ 24
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#define ICP_QAT_HW_AES_256_KEY_SZ 32
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#define ICP_QAT_HW_AES_128_F8_KEY_SZ (ICP_QAT_HW_AES_128_KEY_SZ * \
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QAT_CIPHER_MODE_F8_KEY_SZ_MULT)
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#define ICP_QAT_HW_AES_192_F8_KEY_SZ (ICP_QAT_HW_AES_192_KEY_SZ * \
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QAT_CIPHER_MODE_F8_KEY_SZ_MULT)
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#define ICP_QAT_HW_AES_256_F8_KEY_SZ (ICP_QAT_HW_AES_256_KEY_SZ * \
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QAT_CIPHER_MODE_F8_KEY_SZ_MULT)
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#define ICP_QAT_HW_AES_128_XTS_KEY_SZ (ICP_QAT_HW_AES_128_KEY_SZ * \
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QAT_CIPHER_MODE_XTS_KEY_SZ_MULT)
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#define ICP_QAT_HW_AES_256_XTS_KEY_SZ (ICP_QAT_HW_AES_256_KEY_SZ * \
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QAT_CIPHER_MODE_XTS_KEY_SZ_MULT)
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#define ICP_QAT_HW_KASUMI_KEY_SZ 16
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#define ICP_QAT_HW_KASUMI_F8_KEY_SZ (ICP_QAT_HW_KASUMI_KEY_SZ * \
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QAT_CIPHER_MODE_F8_KEY_SZ_MULT)
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#define ICP_QAT_HW_AES_128_XTS_KEY_SZ (ICP_QAT_HW_AES_128_KEY_SZ * \
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QAT_CIPHER_MODE_XTS_KEY_SZ_MULT)
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#define ICP_QAT_HW_AES_256_XTS_KEY_SZ (ICP_QAT_HW_AES_256_KEY_SZ * \
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QAT_CIPHER_MODE_XTS_KEY_SZ_MULT)
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#define ICP_QAT_HW_ARC4_KEY_SZ 256
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#define ICP_QAT_HW_SNOW_3G_UEA2_KEY_SZ 16
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#define ICP_QAT_HW_SNOW_3G_UEA2_IV_SZ 16
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#define ICP_QAT_HW_ZUC_3G_EEA3_KEY_SZ 16
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#define ICP_QAT_HW_ZUC_3G_EEA3_IV_SZ 16
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#define ICP_QAT_HW_MODE_F8_NUM_REG_TO_CLEAR 2
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#define INIT_SHRAM_CONSTANTS_TABLE_SZ 1024
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struct icp_qat_hw_cipher_aes256_f8 {
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struct icp_qat_hw_cipher_config cipher_config;
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uint8_t key[ICP_QAT_HW_AES_256_F8_KEY_SZ];
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};
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struct icp_qat_hw_cipher_algo_blk {
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struct icp_qat_hw_cipher_aes256_f8 aes;
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} __aligned(64);
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#endif
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