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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version you should have received a copy of the gnu general public license along with this program if not write to the free software foundation inc 675 mass ave cambridge ma 02139 usa extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 35 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Armijn Hemel <armijn@tjaldur.nl> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.655028468@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
233 lines
5.4 KiB
C
233 lines
5.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Xilinx SLCR driver
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*
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* Copyright (c) 2011-2013 Xilinx Inc.
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*/
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#include <linux/io.h>
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#include <linux/reboot.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of_address.h>
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#include <linux/regmap.h>
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#include <linux/clk/zynq.h>
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#include "common.h"
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/* register offsets */
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#define SLCR_UNLOCK_OFFSET 0x8 /* SCLR unlock register */
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#define SLCR_PS_RST_CTRL_OFFSET 0x200 /* PS Software Reset Control */
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#define SLCR_A9_CPU_RST_CTRL_OFFSET 0x244 /* CPU Software Reset Control */
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#define SLCR_REBOOT_STATUS_OFFSET 0x258 /* PS Reboot Status */
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#define SLCR_PSS_IDCODE 0x530 /* PS IDCODE */
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#define SLCR_L2C_RAM 0xA1C /* L2C_RAM in AR#54190 */
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#define SLCR_UNLOCK_MAGIC 0xDF0D
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#define SLCR_A9_CPU_CLKSTOP 0x10
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#define SLCR_A9_CPU_RST 0x1
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#define SLCR_PSS_IDCODE_DEVICE_SHIFT 12
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#define SLCR_PSS_IDCODE_DEVICE_MASK 0x1F
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static void __iomem *zynq_slcr_base;
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static struct regmap *zynq_slcr_regmap;
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/**
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* zynq_slcr_write - Write to a register in SLCR block
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*
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* @val: Value to write to the register
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* @offset: Register offset in SLCR block
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*
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* Return: a negative value on error, 0 on success
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*/
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static int zynq_slcr_write(u32 val, u32 offset)
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{
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return regmap_write(zynq_slcr_regmap, offset, val);
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}
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/**
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* zynq_slcr_read - Read a register in SLCR block
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*
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* @val: Pointer to value to be read from SLCR
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* @offset: Register offset in SLCR block
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*
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* Return: a negative value on error, 0 on success
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*/
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static int zynq_slcr_read(u32 *val, u32 offset)
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{
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return regmap_read(zynq_slcr_regmap, offset, val);
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}
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/**
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* zynq_slcr_unlock - Unlock SLCR registers
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*
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* Return: a negative value on error, 0 on success
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*/
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static inline int zynq_slcr_unlock(void)
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{
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zynq_slcr_write(SLCR_UNLOCK_MAGIC, SLCR_UNLOCK_OFFSET);
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return 0;
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}
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/**
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* zynq_slcr_get_device_id - Read device code id
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*
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* Return: Device code id
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*/
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u32 zynq_slcr_get_device_id(void)
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{
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u32 val;
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zynq_slcr_read(&val, SLCR_PSS_IDCODE);
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val >>= SLCR_PSS_IDCODE_DEVICE_SHIFT;
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val &= SLCR_PSS_IDCODE_DEVICE_MASK;
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return val;
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}
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/**
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* zynq_slcr_system_restart - Restart the entire system.
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*
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* @nb: Pointer to restart notifier block (unused)
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* @action: Reboot mode (unused)
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* @data: Restart handler private data (unused)
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*
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* Return: 0 always
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*/
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static
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int zynq_slcr_system_restart(struct notifier_block *nb,
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unsigned long action, void *data)
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{
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u32 reboot;
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/*
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* Clear 0x0F000000 bits of reboot status register to workaround
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* the FSBL not loading the bitstream after soft-reboot
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* This is a temporary solution until we know more.
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*/
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zynq_slcr_read(&reboot, SLCR_REBOOT_STATUS_OFFSET);
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zynq_slcr_write(reboot & 0xF0FFFFFF, SLCR_REBOOT_STATUS_OFFSET);
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zynq_slcr_write(1, SLCR_PS_RST_CTRL_OFFSET);
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return 0;
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}
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static struct notifier_block zynq_slcr_restart_nb = {
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.notifier_call = zynq_slcr_system_restart,
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.priority = 192,
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};
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/**
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* zynq_slcr_cpu_start - Start cpu
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* @cpu: cpu number
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*/
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void zynq_slcr_cpu_start(int cpu)
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{
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u32 reg;
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zynq_slcr_read(®, SLCR_A9_CPU_RST_CTRL_OFFSET);
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reg &= ~(SLCR_A9_CPU_RST << cpu);
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zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
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reg &= ~(SLCR_A9_CPU_CLKSTOP << cpu);
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zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
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zynq_slcr_cpu_state_write(cpu, false);
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}
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/**
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* zynq_slcr_cpu_stop - Stop cpu
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* @cpu: cpu number
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*/
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void zynq_slcr_cpu_stop(int cpu)
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{
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u32 reg;
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zynq_slcr_read(®, SLCR_A9_CPU_RST_CTRL_OFFSET);
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reg |= (SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu;
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zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
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}
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/**
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* zynq_slcr_cpu_state - Read/write cpu state
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* @cpu: cpu number
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*
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* SLCR_REBOOT_STATUS save upper 2 bits (31/30 cpu states for cpu0 and cpu1)
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* 0 means cpu is running, 1 cpu is going to die.
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*
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* Return: true if cpu is running, false if cpu is going to die
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*/
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bool zynq_slcr_cpu_state_read(int cpu)
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{
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u32 state;
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state = readl(zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
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state &= 1 << (31 - cpu);
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return !state;
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}
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/**
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* zynq_slcr_cpu_state - Read/write cpu state
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* @cpu: cpu number
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* @die: cpu state - true if cpu is going to die
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*
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* SLCR_REBOOT_STATUS save upper 2 bits (31/30 cpu states for cpu0 and cpu1)
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* 0 means cpu is running, 1 cpu is going to die.
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*/
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void zynq_slcr_cpu_state_write(int cpu, bool die)
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{
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u32 state, mask;
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state = readl(zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
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mask = 1 << (31 - cpu);
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if (die)
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state |= mask;
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else
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state &= ~mask;
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writel(state, zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
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}
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/**
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* zynq_early_slcr_init - Early slcr init function
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*
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* Return: 0 on success, negative errno otherwise.
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*
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* Called very early during boot from platform code to unlock SLCR.
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*/
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int __init zynq_early_slcr_init(void)
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{
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struct device_node *np;
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np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-slcr");
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if (!np) {
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pr_err("%s: no slcr node found\n", __func__);
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BUG();
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}
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zynq_slcr_base = of_iomap(np, 0);
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if (!zynq_slcr_base) {
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pr_err("%s: Unable to map I/O memory\n", __func__);
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BUG();
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}
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np->data = (__force void *)zynq_slcr_base;
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zynq_slcr_regmap = syscon_regmap_lookup_by_compatible("xlnx,zynq-slcr");
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if (IS_ERR(zynq_slcr_regmap)) {
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pr_err("%s: failed to find zynq-slcr\n", __func__);
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return -ENODEV;
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}
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/* unlock the SLCR so that registers can be changed */
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zynq_slcr_unlock();
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/* See AR#54190 design advisory */
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regmap_update_bits(zynq_slcr_regmap, SLCR_L2C_RAM, 0x70707, 0x20202);
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register_restart_handler(&zynq_slcr_restart_nb);
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pr_info("%pOFn mapped to %p\n", np, zynq_slcr_base);
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of_node_put(np);
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return 0;
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}
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