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0162818804
* 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86, cpu: Fix detection of Celeron Covington stepping A1 and B0 Documentation, ABI: Update L3 cache index disable text x86, AMD, cacheinfo: Fix L3 cache index disable checks x86, AMD, cacheinfo: Fix fallout caused by max3 conversion x86, cpu: Change NOP selection for certain Intel CPUs x86, cpu: Clean up and unify the NOP selection infrastructure x86, percpu: Use ASM_NOP4 instead of hardcoding P6_NOP4 x86, cpu: Move AMD Elan Kconfig under "Processor family" Fix up trivial conflicts in alternative handling (commitdc326fca2b"x86, cpu: Clean up and unify the NOP selection infrastructure" removed some hacky 5-byte instruction stuff, while commitd430d3d7e6"jump label: Introduce static_branch() interface" renamed HAVE_JUMP_LABEL to CONFIG_JUMP_LABEL in the code that went away)
194 lines
6.6 KiB
C
194 lines
6.6 KiB
C
#ifndef _ASM_X86_ALTERNATIVE_H
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#define _ASM_X86_ALTERNATIVE_H
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#include <linux/types.h>
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#include <linux/stddef.h>
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#include <linux/stringify.h>
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#include <asm/asm.h>
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/*
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* Alternative inline assembly for SMP.
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*
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* The LOCK_PREFIX macro defined here replaces the LOCK and
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* LOCK_PREFIX macros used everywhere in the source tree.
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*
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* SMP alternatives use the same data structures as the other
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* alternatives and the X86_FEATURE_UP flag to indicate the case of a
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* UP system running a SMP kernel. The existing apply_alternatives()
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* works fine for patching a SMP kernel for UP.
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*
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* The SMP alternative tables can be kept after boot and contain both
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* UP and SMP versions of the instructions to allow switching back to
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* SMP at runtime, when hotplugging in a new CPU, which is especially
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* useful in virtualized environments.
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*
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* The very common lock prefix is handled as special case in a
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* separate table which is a pure address list without replacement ptr
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* and size information. That keeps the table sizes small.
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*/
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#ifdef CONFIG_SMP
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#define LOCK_PREFIX_HERE \
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".section .smp_locks,\"a\"\n" \
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".balign 4\n" \
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".long 671f - .\n" /* offset */ \
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".previous\n" \
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"671:"
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#define LOCK_PREFIX LOCK_PREFIX_HERE "\n\tlock; "
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#else /* ! CONFIG_SMP */
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#define LOCK_PREFIX_HERE ""
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#define LOCK_PREFIX ""
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#endif
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struct alt_instr {
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u8 *instr; /* original instruction */
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u8 *replacement;
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u16 cpuid; /* cpuid bit set for replacement */
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u8 instrlen; /* length of original instruction */
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u8 replacementlen; /* length of new instruction, <= instrlen */
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#ifdef CONFIG_X86_64
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u32 pad2;
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#endif
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};
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extern void alternative_instructions(void);
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extern void apply_alternatives(struct alt_instr *start, struct alt_instr *end);
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struct module;
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#ifdef CONFIG_SMP
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extern void alternatives_smp_module_add(struct module *mod, char *name,
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void *locks, void *locks_end,
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void *text, void *text_end);
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extern void alternatives_smp_module_del(struct module *mod);
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extern void alternatives_smp_switch(int smp);
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extern int alternatives_text_reserved(void *start, void *end);
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extern bool skip_smp_alternatives;
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#else
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static inline void alternatives_smp_module_add(struct module *mod, char *name,
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void *locks, void *locks_end,
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void *text, void *text_end) {}
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static inline void alternatives_smp_module_del(struct module *mod) {}
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static inline void alternatives_smp_switch(int smp) {}
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static inline int alternatives_text_reserved(void *start, void *end)
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{
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return 0;
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}
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#endif /* CONFIG_SMP */
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/* alternative assembly primitive: */
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#define ALTERNATIVE(oldinstr, newinstr, feature) \
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\
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"661:\n\t" oldinstr "\n662:\n" \
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".section .altinstructions,\"a\"\n" \
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_ASM_ALIGN "\n" \
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_ASM_PTR "661b\n" /* label */ \
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_ASM_PTR "663f\n" /* new instruction */ \
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" .word " __stringify(feature) "\n" /* feature bit */ \
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" .byte 662b-661b\n" /* sourcelen */ \
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" .byte 664f-663f\n" /* replacementlen */ \
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".previous\n" \
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".section .discard,\"aw\",@progbits\n" \
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" .byte 0xff + (664f-663f) - (662b-661b)\n" /* rlen <= slen */ \
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".previous\n" \
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".section .altinstr_replacement, \"ax\"\n" \
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"663:\n\t" newinstr "\n664:\n" /* replacement */ \
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".previous"
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/*
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* This must be included *after* the definition of ALTERNATIVE due to
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* <asm/arch_hweight.h>
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*/
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#include <asm/cpufeature.h>
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/*
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* Alternative instructions for different CPU types or capabilities.
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*
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* This allows to use optimized instructions even on generic binary
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* kernels.
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*
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* length of oldinstr must be longer or equal the length of newinstr
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* It can be padded with nops as needed.
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*
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* For non barrier like inlines please define new variants
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* without volatile and memory clobber.
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*/
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#define alternative(oldinstr, newinstr, feature) \
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asm volatile (ALTERNATIVE(oldinstr, newinstr, feature) : : : "memory")
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/*
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* Alternative inline assembly with input.
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*
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* Pecularities:
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* No memory clobber here.
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* Argument numbers start with 1.
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* Best is to use constraints that are fixed size (like (%1) ... "r")
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* If you use variable sized constraints like "m" or "g" in the
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* replacement make sure to pad to the worst case length.
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* Leaving an unused argument 0 to keep API compatibility.
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*/
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#define alternative_input(oldinstr, newinstr, feature, input...) \
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asm volatile (ALTERNATIVE(oldinstr, newinstr, feature) \
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: : "i" (0), ## input)
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/* Like alternative_input, but with a single output argument */
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#define alternative_io(oldinstr, newinstr, feature, output, input...) \
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asm volatile (ALTERNATIVE(oldinstr, newinstr, feature) \
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: output : "i" (0), ## input)
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/* Like alternative_io, but for replacing a direct call with another one. */
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#define alternative_call(oldfunc, newfunc, feature, output, input...) \
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asm volatile (ALTERNATIVE("call %P[old]", "call %P[new]", feature) \
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: output : [old] "i" (oldfunc), [new] "i" (newfunc), ## input)
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/*
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* use this macro(s) if you need more than one output parameter
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* in alternative_io
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*/
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#define ASM_OUTPUT2(a...) a
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struct paravirt_patch_site;
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#ifdef CONFIG_PARAVIRT
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void apply_paravirt(struct paravirt_patch_site *start,
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struct paravirt_patch_site *end);
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#else
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static inline void apply_paravirt(struct paravirt_patch_site *start,
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struct paravirt_patch_site *end)
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{}
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#define __parainstructions NULL
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#define __parainstructions_end NULL
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#endif
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extern void *text_poke_early(void *addr, const void *opcode, size_t len);
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/*
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* Clear and restore the kernel write-protection flag on the local CPU.
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* Allows the kernel to edit read-only pages.
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* Side-effect: any interrupt handler running between save and restore will have
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* the ability to write to read-only pages.
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*
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* Warning:
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* Code patching in the UP case is safe if NMIs and MCE handlers are stopped and
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* no thread can be preempted in the instructions being modified (no iret to an
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* invalid instruction possible) or if the instructions are changed from a
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* consistent state to another consistent state atomically.
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* More care must be taken when modifying code in the SMP case because of
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* Intel's errata. text_poke_smp() takes care that errata, but still
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* doesn't support NMI/MCE handler code modifying.
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* On the local CPU you need to be protected again NMI or MCE handlers seeing an
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* inconsistent instruction while you patch.
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*/
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struct text_poke_param {
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void *addr;
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const void *opcode;
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size_t len;
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};
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extern void *text_poke(void *addr, const void *opcode, size_t len);
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extern void *text_poke_smp(void *addr, const void *opcode, size_t len);
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extern void text_poke_smp_batch(struct text_poke_param *params, int n);
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#endif /* _ASM_X86_ALTERNATIVE_H */
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