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549f3ae1be
This patch adds necessary DT nodes for pcie controllers and miphys for SPEAr13xx SoCs. SPEAr1310 has 3 PCIe ports and SPEAr1340 has 1, which are multiplexed with ahci/sata pins. By default evaluation board of both controller works in ahci mode. Because of this, these nodes are marked "disabled" by default. In order to use pcie controller on evaluation boards do necessary modifications on board and enable (By replacing "disabled" with "okay") pcie and miphy from respective 'evb' dtsi file. Phy specific initialization was previously done from spear1340.c, which isn't required anymore as we have separate drivers for it. Remove it. Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Pratyush Anand <pratyush.anand@st.com> Signed-off-by: Mohit Kumar <mohit.kumar@st.com> [viresh: fixed logs/cclist/checkpatch warnings, clubbed multiple patches into one] Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
344 lines
7.4 KiB
Plaintext
344 lines
7.4 KiB
Plaintext
/*
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* DTS file for all SPEAr13xx SoCs
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*
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* Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/include/ "skeleton.dtsi"
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/ {
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <0>;
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next-level-cache = <&L2>;
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};
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cpu@1 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <1>;
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next-level-cache = <&L2>;
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};
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};
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gic: interrupt-controller@ec801000 {
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compatible = "arm,cortex-a9-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = < 0xec801000 0x1000 >,
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< 0xec800100 0x0100 >;
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};
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pmu {
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compatible = "arm,cortex-a9-pmu";
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interrupts = <0 6 0x04
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0 7 0x04>;
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};
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L2: l2-cache {
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compatible = "arm,pl310-cache";
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reg = <0xed000000 0x1000>;
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cache-unified;
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cache-level = <2>;
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};
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memory {
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name = "memory";
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device_type = "memory";
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reg = <0 0x40000000>;
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};
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chosen {
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bootargs = "console=ttyAMA0,115200";
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};
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cpufreq {
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compatible = "st,cpufreq-spear";
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cpufreq_tbl = < 166000
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200000
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250000
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300000
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400000
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500000
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600000 >;
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status = "disabled";
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};
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ahb {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0x50000000 0x50000000 0x10000000
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0x80000000 0x80000000 0x20000000
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0xb0000000 0xb0000000 0x22000000
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0xd8000000 0xd8000000 0x01000000
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0xe0000000 0xe0000000 0x10000000>;
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sdhci@b3000000 {
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compatible = "st,sdhci-spear";
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reg = <0xb3000000 0x100>;
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interrupts = <0 28 0x4>;
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status = "disabled";
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};
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cf@b2800000 {
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compatible = "arasan,cf-spear1340";
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reg = <0xb2800000 0x1000>;
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interrupts = <0 29 0x4>;
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status = "disabled";
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dmas = <&dwdma0 0 0 0 0>;
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dma-names = "data";
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};
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dwdma0: dma@ea800000 {
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compatible = "snps,dma-spear1340";
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reg = <0xea800000 0x1000>;
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interrupts = <0 19 0x4>;
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status = "disabled";
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dma-channels = <8>;
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#dma-cells = <3>;
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dma-requests = <32>;
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chan_allocation_order = <1>;
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chan_priority = <1>;
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block_size = <0xfff>;
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dma-masters = <2>;
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data_width = <3 3 0 0>;
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};
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dma@eb000000 {
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compatible = "snps,dma-spear1340";
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reg = <0xeb000000 0x1000>;
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interrupts = <0 59 0x4>;
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status = "disabled";
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dma-requests = <32>;
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dma-channels = <8>;
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dma-masters = <2>;
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#dma-cells = <3>;
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chan_allocation_order = <1>;
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chan_priority = <1>;
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block_size = <0xfff>;
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data_width = <3 3 0 0>;
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};
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fsmc: flash@b0000000 {
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compatible = "st,spear600-fsmc-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0xb0000000 0x1000 /* FSMC Register*/
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0xb0800000 0x0010 /* NAND Base DATA */
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0xb0820000 0x0010 /* NAND Base ADDR */
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0xb0810000 0x0010>; /* NAND Base CMD */
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reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
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interrupts = <0 20 0x4
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0 21 0x4
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0 22 0x4
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0 23 0x4>;
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st,mode = <2>;
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status = "disabled";
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};
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gmac0: eth@e2000000 {
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compatible = "st,spear600-gmac";
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reg = <0xe2000000 0x8000>;
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interrupts = <0 33 0x4
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0 34 0x4>;
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interrupt-names = "macirq", "eth_wake_irq";
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status = "disabled";
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};
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pcm {
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compatible = "st,pcm-audio";
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#address-cells = <0>;
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#size-cells = <0>;
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status = "disabled";
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};
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smi: flash@ea000000 {
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compatible = "st,spear600-smi";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0xea000000 0x1000>;
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interrupts = <0 30 0x4>;
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status = "disabled";
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};
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ehci@e4800000 {
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compatible = "st,spear600-ehci", "usb-ehci";
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reg = <0xe4800000 0x1000>;
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interrupts = <0 64 0x4>;
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usbh0_id = <0>;
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status = "disabled";
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};
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ehci@e5800000 {
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compatible = "st,spear600-ehci", "usb-ehci";
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reg = <0xe5800000 0x1000>;
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interrupts = <0 66 0x4>;
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usbh1_id = <1>;
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status = "disabled";
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};
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ohci@e4000000 {
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compatible = "st,spear600-ohci", "usb-ohci";
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reg = <0xe4000000 0x1000>;
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interrupts = <0 65 0x4>;
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usbh0_id = <0>;
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status = "disabled";
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};
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ohci@e5000000 {
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compatible = "st,spear600-ohci", "usb-ohci";
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reg = <0xe5000000 0x1000>;
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interrupts = <0 67 0x4>;
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usbh1_id = <1>;
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status = "disabled";
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};
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apb {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0x50000000 0x50000000 0x10000000
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0xb0000000 0xb0000000 0x10000000
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0xd0000000 0xd0000000 0x02000000
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0xd8000000 0xd8000000 0x01000000
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0xe0000000 0xe0000000 0x10000000>;
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misc: syscon@e0700000 {
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compatible = "st,spear1340-misc", "syscon";
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reg = <0xe0700000 0x1000>;
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};
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gpio0: gpio@e0600000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0xe0600000 0x1000>;
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interrupts = <0 24 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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status = "disabled";
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};
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gpio1: gpio@e0680000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0xe0680000 0x1000>;
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interrupts = <0 25 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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status = "disabled";
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};
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kbd@e0300000 {
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compatible = "st,spear300-kbd";
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reg = <0xe0300000 0x1000>;
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interrupts = <0 52 0x4>;
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status = "disabled";
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};
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i2c0: i2c@e0280000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-i2c";
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reg = <0xe0280000 0x1000>;
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interrupts = <0 41 0x4>;
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status = "disabled";
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};
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i2s@e0180000 {
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compatible = "st,designware-i2s";
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reg = <0xe0180000 0x1000>;
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interrupt-names = "play_irq", "record_irq";
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interrupts = <0 10 0x4
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0 11 0x4 >;
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status = "disabled";
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};
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i2s@e0200000 {
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compatible = "st,designware-i2s";
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reg = <0xe0200000 0x1000>;
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interrupt-names = "play_irq", "record_irq";
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interrupts = <0 26 0x4
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0 53 0x4>;
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status = "disabled";
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};
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spi0: spi@e0100000 {
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compatible = "arm,pl022", "arm,primecell";
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reg = <0xe0100000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 31 0x4>;
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status = "disabled";
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dmas = <&dwdma0 0x2000 0 0 0>, /* 0x4 << 11 */
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<&dwdma0 0x0280 0 0 0>; /* 0x5 << 7 */
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dma-names = "tx", "rx";
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};
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rtc@e0580000 {
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compatible = "st,spear600-rtc";
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reg = <0xe0580000 0x1000>;
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interrupts = <0 36 0x4>;
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status = "disabled";
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};
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serial@e0000000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0xe0000000 0x1000>;
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interrupts = <0 35 0x4>;
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status = "disabled";
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};
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adc@e0080000 {
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compatible = "st,spear600-adc";
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reg = <0xe0080000 0x1000>;
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interrupts = <0 12 0x4>;
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status = "disabled";
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};
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timer@e0380000 {
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compatible = "st,spear-timer";
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reg = <0xe0380000 0x400>;
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interrupts = <0 37 0x4>;
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};
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timer@ec800600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0xec800600 0x20>;
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interrupts = <1 13 0x4>;
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status = "disabled";
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};
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wdt@ec800620 {
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compatible = "arm,cortex-a9-twd-wdt";
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reg = <0xec800620 0x20>;
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status = "disabled";
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};
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thermal@e07008c4 {
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compatible = "st,thermal-spear1340";
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reg = <0xe07008c4 0x4>;
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thermal_flags = <0x7000>;
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};
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};
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};
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};
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