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a87010ef32
SiRF internal interrupts are using level trigger. we need to tell the irq core this information. otherwise, we might get some problems as below 1. disable_irq(n) here irq core will mark the disabled flag but still keep the irq enabled due to involved lazy-disable 2. doing someting after disable_irq(n) in step 2, if one interrupt n comes, irq core will mark it as pending and mask the HW interrupt really. we name the coming interrupt as "X". 3. enable_irq(n) this will unmask the interrupt, so the level-trigger HW interrupt will come again, irq_handler will enter as "E1". after that, irq core will also check whether irq n is pending, if yes, and pending interrupt is not level-trigger, irq core will execute the pending irq_handler. so if we don't set the IRQ_LEVEL flag here, irq core will execute pending X again as "E2", but actually the pending interrupt has been handled by "E1". that makes a level-trigger HW interrupt is executed twice. here we fix the issue to avoid redundant interrupt overload. Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Huayi Li <Huayi.Li@csr.com> Signed-off-by: Olof Johansson <olof@lixom.net> |
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| .. | ||
| exynos-combiner.c | ||
| irq-armada-370-xp.c | ||
| irq-bcm2835.c | ||
| irq-gic.c | ||
| irq-imgpdc.c | ||
| irq-metag-ext.c | ||
| irq-metag.c | ||
| irq-mmp.c | ||
| irq-moxart.c | ||
| irq-mxs.c | ||
| irq-nvic.c | ||
| irq-orion.c | ||
| irq-renesas-intc-irqpin.c | ||
| irq-renesas-irqc.c | ||
| irq-s3c24xx.c | ||
| irq-sirfsoc.c | ||
| irq-sun4i.c | ||
| irq-tb10x.c | ||
| irq-versatile-fpga.c | ||
| irq-vic.c | ||
| irq-vt8500.c | ||
| irqchip.c | ||
| irqchip.h | ||
| Kconfig | ||
| Makefile | ||
| spear-shirq.c | ||