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50b7d22079
In order to use PCI P2P memory the pci_p2pmem_map_sg() function must be called to map the correct PCI bus address. To do this, check the first page in the scatter list to see if it is P2P memory or not. At the moment, scatter lists that contain P2P memory must be homogeneous so if the first page is P2P the entire SGL should be P2P. Signed-off-by: Logan Gunthorpe <logang@deltatee.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Sagi Grimberg <sagi@grimberg.me>
753 lines
21 KiB
C
753 lines
21 KiB
C
/*
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* Copyright (c) 2016 HGST, a Western Digital Company.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/moduleparam.h>
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#include <linux/slab.h>
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#include <linux/pci-p2pdma.h>
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#include <rdma/mr_pool.h>
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#include <rdma/rw.h>
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enum {
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RDMA_RW_SINGLE_WR,
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RDMA_RW_MULTI_WR,
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RDMA_RW_MR,
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RDMA_RW_SIG_MR,
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};
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static bool rdma_rw_force_mr;
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module_param_named(force_mr, rdma_rw_force_mr, bool, 0);
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MODULE_PARM_DESC(force_mr, "Force usage of MRs for RDMA READ/WRITE operations");
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/*
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* Check if the device might use memory registration. This is currently only
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* true for iWarp devices. In the future we can hopefully fine tune this based
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* on HCA driver input.
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*/
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static inline bool rdma_rw_can_use_mr(struct ib_device *dev, u8 port_num)
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{
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if (rdma_protocol_iwarp(dev, port_num))
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return true;
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if (unlikely(rdma_rw_force_mr))
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return true;
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return false;
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}
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/*
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* Check if the device will use memory registration for this RW operation.
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* We currently always use memory registrations for iWarp RDMA READs, and
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* have a debug option to force usage of MRs.
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*
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* XXX: In the future we can hopefully fine tune this based on HCA driver
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* input.
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*/
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static inline bool rdma_rw_io_needs_mr(struct ib_device *dev, u8 port_num,
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enum dma_data_direction dir, int dma_nents)
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{
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if (rdma_protocol_iwarp(dev, port_num) && dir == DMA_FROM_DEVICE)
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return true;
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if (unlikely(rdma_rw_force_mr))
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return true;
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return false;
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}
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static inline u32 rdma_rw_fr_page_list_len(struct ib_device *dev)
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{
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/* arbitrary limit to avoid allocating gigantic resources */
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return min_t(u32, dev->attrs.max_fast_reg_page_list_len, 256);
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}
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/* Caller must have zero-initialized *reg. */
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static int rdma_rw_init_one_mr(struct ib_qp *qp, u8 port_num,
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struct rdma_rw_reg_ctx *reg, struct scatterlist *sg,
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u32 sg_cnt, u32 offset)
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{
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u32 pages_per_mr = rdma_rw_fr_page_list_len(qp->pd->device);
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u32 nents = min(sg_cnt, pages_per_mr);
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int count = 0, ret;
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reg->mr = ib_mr_pool_get(qp, &qp->rdma_mrs);
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if (!reg->mr)
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return -EAGAIN;
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if (reg->mr->need_inval) {
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reg->inv_wr.opcode = IB_WR_LOCAL_INV;
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reg->inv_wr.ex.invalidate_rkey = reg->mr->lkey;
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reg->inv_wr.next = ®->reg_wr.wr;
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count++;
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} else {
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reg->inv_wr.next = NULL;
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}
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ret = ib_map_mr_sg(reg->mr, sg, nents, &offset, PAGE_SIZE);
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if (ret < 0 || ret < nents) {
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ib_mr_pool_put(qp, &qp->rdma_mrs, reg->mr);
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return -EINVAL;
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}
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reg->reg_wr.wr.opcode = IB_WR_REG_MR;
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reg->reg_wr.mr = reg->mr;
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reg->reg_wr.access = IB_ACCESS_LOCAL_WRITE;
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if (rdma_protocol_iwarp(qp->device, port_num))
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reg->reg_wr.access |= IB_ACCESS_REMOTE_WRITE;
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count++;
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reg->sge.addr = reg->mr->iova;
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reg->sge.length = reg->mr->length;
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return count;
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}
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static int rdma_rw_init_mr_wrs(struct rdma_rw_ctx *ctx, struct ib_qp *qp,
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u8 port_num, struct scatterlist *sg, u32 sg_cnt, u32 offset,
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u64 remote_addr, u32 rkey, enum dma_data_direction dir)
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{
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struct rdma_rw_reg_ctx *prev = NULL;
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u32 pages_per_mr = rdma_rw_fr_page_list_len(qp->pd->device);
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int i, j, ret = 0, count = 0;
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ctx->nr_ops = (sg_cnt + pages_per_mr - 1) / pages_per_mr;
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ctx->reg = kcalloc(ctx->nr_ops, sizeof(*ctx->reg), GFP_KERNEL);
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if (!ctx->reg) {
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ret = -ENOMEM;
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goto out;
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}
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for (i = 0; i < ctx->nr_ops; i++) {
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struct rdma_rw_reg_ctx *reg = &ctx->reg[i];
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u32 nents = min(sg_cnt, pages_per_mr);
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ret = rdma_rw_init_one_mr(qp, port_num, reg, sg, sg_cnt,
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offset);
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if (ret < 0)
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goto out_free;
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count += ret;
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if (prev) {
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if (reg->mr->need_inval)
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prev->wr.wr.next = ®->inv_wr;
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else
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prev->wr.wr.next = ®->reg_wr.wr;
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}
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reg->reg_wr.wr.next = ®->wr.wr;
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reg->wr.wr.sg_list = ®->sge;
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reg->wr.wr.num_sge = 1;
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reg->wr.remote_addr = remote_addr;
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reg->wr.rkey = rkey;
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if (dir == DMA_TO_DEVICE) {
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reg->wr.wr.opcode = IB_WR_RDMA_WRITE;
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} else if (!rdma_cap_read_inv(qp->device, port_num)) {
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reg->wr.wr.opcode = IB_WR_RDMA_READ;
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} else {
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reg->wr.wr.opcode = IB_WR_RDMA_READ_WITH_INV;
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reg->wr.wr.ex.invalidate_rkey = reg->mr->lkey;
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}
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count++;
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remote_addr += reg->sge.length;
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sg_cnt -= nents;
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for (j = 0; j < nents; j++)
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sg = sg_next(sg);
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prev = reg;
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offset = 0;
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}
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if (prev)
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prev->wr.wr.next = NULL;
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ctx->type = RDMA_RW_MR;
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return count;
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out_free:
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while (--i >= 0)
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ib_mr_pool_put(qp, &qp->rdma_mrs, ctx->reg[i].mr);
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kfree(ctx->reg);
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out:
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return ret;
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}
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static int rdma_rw_init_map_wrs(struct rdma_rw_ctx *ctx, struct ib_qp *qp,
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struct scatterlist *sg, u32 sg_cnt, u32 offset,
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u64 remote_addr, u32 rkey, enum dma_data_direction dir)
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{
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struct ib_device *dev = qp->pd->device;
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u32 max_sge = dir == DMA_TO_DEVICE ? qp->max_write_sge :
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qp->max_read_sge;
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struct ib_sge *sge;
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u32 total_len = 0, i, j;
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ctx->nr_ops = DIV_ROUND_UP(sg_cnt, max_sge);
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ctx->map.sges = sge = kcalloc(sg_cnt, sizeof(*sge), GFP_KERNEL);
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if (!ctx->map.sges)
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goto out;
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ctx->map.wrs = kcalloc(ctx->nr_ops, sizeof(*ctx->map.wrs), GFP_KERNEL);
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if (!ctx->map.wrs)
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goto out_free_sges;
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for (i = 0; i < ctx->nr_ops; i++) {
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struct ib_rdma_wr *rdma_wr = &ctx->map.wrs[i];
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u32 nr_sge = min(sg_cnt, max_sge);
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if (dir == DMA_TO_DEVICE)
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rdma_wr->wr.opcode = IB_WR_RDMA_WRITE;
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else
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rdma_wr->wr.opcode = IB_WR_RDMA_READ;
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rdma_wr->remote_addr = remote_addr + total_len;
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rdma_wr->rkey = rkey;
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rdma_wr->wr.num_sge = nr_sge;
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rdma_wr->wr.sg_list = sge;
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for (j = 0; j < nr_sge; j++, sg = sg_next(sg)) {
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sge->addr = ib_sg_dma_address(dev, sg) + offset;
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sge->length = ib_sg_dma_len(dev, sg) - offset;
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sge->lkey = qp->pd->local_dma_lkey;
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total_len += sge->length;
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sge++;
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sg_cnt--;
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offset = 0;
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}
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rdma_wr->wr.next = i + 1 < ctx->nr_ops ?
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&ctx->map.wrs[i + 1].wr : NULL;
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}
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ctx->type = RDMA_RW_MULTI_WR;
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return ctx->nr_ops;
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out_free_sges:
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kfree(ctx->map.sges);
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out:
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return -ENOMEM;
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}
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static int rdma_rw_init_single_wr(struct rdma_rw_ctx *ctx, struct ib_qp *qp,
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struct scatterlist *sg, u32 offset, u64 remote_addr, u32 rkey,
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enum dma_data_direction dir)
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{
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struct ib_device *dev = qp->pd->device;
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struct ib_rdma_wr *rdma_wr = &ctx->single.wr;
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ctx->nr_ops = 1;
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ctx->single.sge.lkey = qp->pd->local_dma_lkey;
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ctx->single.sge.addr = ib_sg_dma_address(dev, sg) + offset;
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ctx->single.sge.length = ib_sg_dma_len(dev, sg) - offset;
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memset(rdma_wr, 0, sizeof(*rdma_wr));
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if (dir == DMA_TO_DEVICE)
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rdma_wr->wr.opcode = IB_WR_RDMA_WRITE;
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else
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rdma_wr->wr.opcode = IB_WR_RDMA_READ;
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rdma_wr->wr.sg_list = &ctx->single.sge;
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rdma_wr->wr.num_sge = 1;
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rdma_wr->remote_addr = remote_addr;
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rdma_wr->rkey = rkey;
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ctx->type = RDMA_RW_SINGLE_WR;
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return 1;
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}
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/**
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* rdma_rw_ctx_init - initialize a RDMA READ/WRITE context
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* @ctx: context to initialize
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* @qp: queue pair to operate on
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* @port_num: port num to which the connection is bound
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* @sg: scatterlist to READ/WRITE from/to
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* @sg_cnt: number of entries in @sg
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* @sg_offset: current byte offset into @sg
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* @remote_addr:remote address to read/write (relative to @rkey)
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* @rkey: remote key to operate on
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* @dir: %DMA_TO_DEVICE for RDMA WRITE, %DMA_FROM_DEVICE for RDMA READ
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*
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* Returns the number of WQEs that will be needed on the workqueue if
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* successful, or a negative error code.
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*/
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int rdma_rw_ctx_init(struct rdma_rw_ctx *ctx, struct ib_qp *qp, u8 port_num,
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struct scatterlist *sg, u32 sg_cnt, u32 sg_offset,
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u64 remote_addr, u32 rkey, enum dma_data_direction dir)
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{
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struct ib_device *dev = qp->pd->device;
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int ret;
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if (is_pci_p2pdma_page(sg_page(sg)))
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ret = pci_p2pdma_map_sg(dev->dma_device, sg, sg_cnt, dir);
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else
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ret = ib_dma_map_sg(dev, sg, sg_cnt, dir);
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if (!ret)
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return -ENOMEM;
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sg_cnt = ret;
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/*
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* Skip to the S/G entry that sg_offset falls into:
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*/
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for (;;) {
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u32 len = ib_sg_dma_len(dev, sg);
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if (sg_offset < len)
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break;
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sg = sg_next(sg);
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sg_offset -= len;
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sg_cnt--;
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}
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ret = -EIO;
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if (WARN_ON_ONCE(sg_cnt == 0))
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goto out_unmap_sg;
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if (rdma_rw_io_needs_mr(qp->device, port_num, dir, sg_cnt)) {
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ret = rdma_rw_init_mr_wrs(ctx, qp, port_num, sg, sg_cnt,
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sg_offset, remote_addr, rkey, dir);
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} else if (sg_cnt > 1) {
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ret = rdma_rw_init_map_wrs(ctx, qp, sg, sg_cnt, sg_offset,
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remote_addr, rkey, dir);
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} else {
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ret = rdma_rw_init_single_wr(ctx, qp, sg, sg_offset,
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remote_addr, rkey, dir);
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}
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if (ret < 0)
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goto out_unmap_sg;
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return ret;
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out_unmap_sg:
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ib_dma_unmap_sg(dev, sg, sg_cnt, dir);
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return ret;
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}
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EXPORT_SYMBOL(rdma_rw_ctx_init);
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/**
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* rdma_rw_ctx_signature_init - initialize a RW context with signature offload
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* @ctx: context to initialize
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* @qp: queue pair to operate on
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* @port_num: port num to which the connection is bound
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* @sg: scatterlist to READ/WRITE from/to
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* @sg_cnt: number of entries in @sg
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* @prot_sg: scatterlist to READ/WRITE protection information from/to
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* @prot_sg_cnt: number of entries in @prot_sg
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* @sig_attrs: signature offloading algorithms
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* @remote_addr:remote address to read/write (relative to @rkey)
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* @rkey: remote key to operate on
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* @dir: %DMA_TO_DEVICE for RDMA WRITE, %DMA_FROM_DEVICE for RDMA READ
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*
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* Returns the number of WQEs that will be needed on the workqueue if
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* successful, or a negative error code.
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*/
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int rdma_rw_ctx_signature_init(struct rdma_rw_ctx *ctx, struct ib_qp *qp,
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u8 port_num, struct scatterlist *sg, u32 sg_cnt,
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struct scatterlist *prot_sg, u32 prot_sg_cnt,
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struct ib_sig_attrs *sig_attrs,
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u64 remote_addr, u32 rkey, enum dma_data_direction dir)
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{
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struct ib_device *dev = qp->pd->device;
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u32 pages_per_mr = rdma_rw_fr_page_list_len(qp->pd->device);
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struct ib_rdma_wr *rdma_wr;
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struct ib_send_wr *prev_wr = NULL;
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int count = 0, ret;
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if (sg_cnt > pages_per_mr || prot_sg_cnt > pages_per_mr) {
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pr_err("SG count too large\n");
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return -EINVAL;
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}
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ret = ib_dma_map_sg(dev, sg, sg_cnt, dir);
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if (!ret)
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return -ENOMEM;
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sg_cnt = ret;
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ret = ib_dma_map_sg(dev, prot_sg, prot_sg_cnt, dir);
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if (!ret) {
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ret = -ENOMEM;
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goto out_unmap_sg;
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}
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prot_sg_cnt = ret;
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ctx->type = RDMA_RW_SIG_MR;
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ctx->nr_ops = 1;
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ctx->sig = kcalloc(1, sizeof(*ctx->sig), GFP_KERNEL);
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if (!ctx->sig) {
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ret = -ENOMEM;
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goto out_unmap_prot_sg;
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}
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ret = rdma_rw_init_one_mr(qp, port_num, &ctx->sig->data, sg, sg_cnt, 0);
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if (ret < 0)
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goto out_free_ctx;
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count += ret;
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prev_wr = &ctx->sig->data.reg_wr.wr;
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ret = rdma_rw_init_one_mr(qp, port_num, &ctx->sig->prot,
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prot_sg, prot_sg_cnt, 0);
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if (ret < 0)
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goto out_destroy_data_mr;
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count += ret;
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if (ctx->sig->prot.inv_wr.next)
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prev_wr->next = &ctx->sig->prot.inv_wr;
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else
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prev_wr->next = &ctx->sig->prot.reg_wr.wr;
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prev_wr = &ctx->sig->prot.reg_wr.wr;
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ctx->sig->sig_mr = ib_mr_pool_get(qp, &qp->sig_mrs);
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if (!ctx->sig->sig_mr) {
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ret = -EAGAIN;
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goto out_destroy_prot_mr;
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}
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if (ctx->sig->sig_mr->need_inval) {
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memset(&ctx->sig->sig_inv_wr, 0, sizeof(ctx->sig->sig_inv_wr));
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ctx->sig->sig_inv_wr.opcode = IB_WR_LOCAL_INV;
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ctx->sig->sig_inv_wr.ex.invalidate_rkey = ctx->sig->sig_mr->rkey;
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prev_wr->next = &ctx->sig->sig_inv_wr;
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prev_wr = &ctx->sig->sig_inv_wr;
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}
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ctx->sig->sig_wr.wr.opcode = IB_WR_REG_SIG_MR;
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ctx->sig->sig_wr.wr.wr_cqe = NULL;
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ctx->sig->sig_wr.wr.sg_list = &ctx->sig->data.sge;
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ctx->sig->sig_wr.wr.num_sge = 1;
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ctx->sig->sig_wr.access_flags = IB_ACCESS_LOCAL_WRITE;
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ctx->sig->sig_wr.sig_attrs = sig_attrs;
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ctx->sig->sig_wr.sig_mr = ctx->sig->sig_mr;
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if (prot_sg_cnt)
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ctx->sig->sig_wr.prot = &ctx->sig->prot.sge;
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prev_wr->next = &ctx->sig->sig_wr.wr;
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prev_wr = &ctx->sig->sig_wr.wr;
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count++;
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ctx->sig->sig_sge.addr = 0;
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ctx->sig->sig_sge.length = ctx->sig->data.sge.length;
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if (sig_attrs->wire.sig_type != IB_SIG_TYPE_NONE)
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ctx->sig->sig_sge.length += ctx->sig->prot.sge.length;
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rdma_wr = &ctx->sig->data.wr;
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rdma_wr->wr.sg_list = &ctx->sig->sig_sge;
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rdma_wr->wr.num_sge = 1;
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rdma_wr->remote_addr = remote_addr;
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rdma_wr->rkey = rkey;
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if (dir == DMA_TO_DEVICE)
|
|
rdma_wr->wr.opcode = IB_WR_RDMA_WRITE;
|
|
else
|
|
rdma_wr->wr.opcode = IB_WR_RDMA_READ;
|
|
prev_wr->next = &rdma_wr->wr;
|
|
prev_wr = &rdma_wr->wr;
|
|
count++;
|
|
|
|
return count;
|
|
|
|
out_destroy_prot_mr:
|
|
if (prot_sg_cnt)
|
|
ib_mr_pool_put(qp, &qp->rdma_mrs, ctx->sig->prot.mr);
|
|
out_destroy_data_mr:
|
|
ib_mr_pool_put(qp, &qp->rdma_mrs, ctx->sig->data.mr);
|
|
out_free_ctx:
|
|
kfree(ctx->sig);
|
|
out_unmap_prot_sg:
|
|
ib_dma_unmap_sg(dev, prot_sg, prot_sg_cnt, dir);
|
|
out_unmap_sg:
|
|
ib_dma_unmap_sg(dev, sg, sg_cnt, dir);
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL(rdma_rw_ctx_signature_init);
|
|
|
|
/*
|
|
* Now that we are going to post the WRs we can update the lkey and need_inval
|
|
* state on the MRs. If we were doing this at init time, we would get double
|
|
* or missing invalidations if a context was initialized but not actually
|
|
* posted.
|
|
*/
|
|
static void rdma_rw_update_lkey(struct rdma_rw_reg_ctx *reg, bool need_inval)
|
|
{
|
|
reg->mr->need_inval = need_inval;
|
|
ib_update_fast_reg_key(reg->mr, ib_inc_rkey(reg->mr->lkey));
|
|
reg->reg_wr.key = reg->mr->lkey;
|
|
reg->sge.lkey = reg->mr->lkey;
|
|
}
|
|
|
|
/**
|
|
* rdma_rw_ctx_wrs - return chain of WRs for a RDMA READ or WRITE operation
|
|
* @ctx: context to operate on
|
|
* @qp: queue pair to operate on
|
|
* @port_num: port num to which the connection is bound
|
|
* @cqe: completion queue entry for the last WR
|
|
* @chain_wr: WR to append to the posted chain
|
|
*
|
|
* Return the WR chain for the set of RDMA READ/WRITE operations described by
|
|
* @ctx, as well as any memory registration operations needed. If @chain_wr
|
|
* is non-NULL the WR it points to will be appended to the chain of WRs posted.
|
|
* If @chain_wr is not set @cqe must be set so that the caller gets a
|
|
* completion notification.
|
|
*/
|
|
struct ib_send_wr *rdma_rw_ctx_wrs(struct rdma_rw_ctx *ctx, struct ib_qp *qp,
|
|
u8 port_num, struct ib_cqe *cqe, struct ib_send_wr *chain_wr)
|
|
{
|
|
struct ib_send_wr *first_wr, *last_wr;
|
|
int i;
|
|
|
|
switch (ctx->type) {
|
|
case RDMA_RW_SIG_MR:
|
|
rdma_rw_update_lkey(&ctx->sig->data, true);
|
|
if (ctx->sig->prot.mr)
|
|
rdma_rw_update_lkey(&ctx->sig->prot, true);
|
|
|
|
ctx->sig->sig_mr->need_inval = true;
|
|
ib_update_fast_reg_key(ctx->sig->sig_mr,
|
|
ib_inc_rkey(ctx->sig->sig_mr->lkey));
|
|
ctx->sig->sig_sge.lkey = ctx->sig->sig_mr->lkey;
|
|
|
|
if (ctx->sig->data.inv_wr.next)
|
|
first_wr = &ctx->sig->data.inv_wr;
|
|
else
|
|
first_wr = &ctx->sig->data.reg_wr.wr;
|
|
last_wr = &ctx->sig->data.wr.wr;
|
|
break;
|
|
case RDMA_RW_MR:
|
|
for (i = 0; i < ctx->nr_ops; i++) {
|
|
rdma_rw_update_lkey(&ctx->reg[i],
|
|
ctx->reg[i].wr.wr.opcode !=
|
|
IB_WR_RDMA_READ_WITH_INV);
|
|
}
|
|
|
|
if (ctx->reg[0].inv_wr.next)
|
|
first_wr = &ctx->reg[0].inv_wr;
|
|
else
|
|
first_wr = &ctx->reg[0].reg_wr.wr;
|
|
last_wr = &ctx->reg[ctx->nr_ops - 1].wr.wr;
|
|
break;
|
|
case RDMA_RW_MULTI_WR:
|
|
first_wr = &ctx->map.wrs[0].wr;
|
|
last_wr = &ctx->map.wrs[ctx->nr_ops - 1].wr;
|
|
break;
|
|
case RDMA_RW_SINGLE_WR:
|
|
first_wr = &ctx->single.wr.wr;
|
|
last_wr = &ctx->single.wr.wr;
|
|
break;
|
|
default:
|
|
BUG();
|
|
}
|
|
|
|
if (chain_wr) {
|
|
last_wr->next = chain_wr;
|
|
} else {
|
|
last_wr->wr_cqe = cqe;
|
|
last_wr->send_flags |= IB_SEND_SIGNALED;
|
|
}
|
|
|
|
return first_wr;
|
|
}
|
|
EXPORT_SYMBOL(rdma_rw_ctx_wrs);
|
|
|
|
/**
|
|
* rdma_rw_ctx_post - post a RDMA READ or RDMA WRITE operation
|
|
* @ctx: context to operate on
|
|
* @qp: queue pair to operate on
|
|
* @port_num: port num to which the connection is bound
|
|
* @cqe: completion queue entry for the last WR
|
|
* @chain_wr: WR to append to the posted chain
|
|
*
|
|
* Post the set of RDMA READ/WRITE operations described by @ctx, as well as
|
|
* any memory registration operations needed. If @chain_wr is non-NULL the
|
|
* WR it points to will be appended to the chain of WRs posted. If @chain_wr
|
|
* is not set @cqe must be set so that the caller gets a completion
|
|
* notification.
|
|
*/
|
|
int rdma_rw_ctx_post(struct rdma_rw_ctx *ctx, struct ib_qp *qp, u8 port_num,
|
|
struct ib_cqe *cqe, struct ib_send_wr *chain_wr)
|
|
{
|
|
struct ib_send_wr *first_wr;
|
|
|
|
first_wr = rdma_rw_ctx_wrs(ctx, qp, port_num, cqe, chain_wr);
|
|
return ib_post_send(qp, first_wr, NULL);
|
|
}
|
|
EXPORT_SYMBOL(rdma_rw_ctx_post);
|
|
|
|
/**
|
|
* rdma_rw_ctx_destroy - release all resources allocated by rdma_rw_ctx_init
|
|
* @ctx: context to release
|
|
* @qp: queue pair to operate on
|
|
* @port_num: port num to which the connection is bound
|
|
* @sg: scatterlist that was used for the READ/WRITE
|
|
* @sg_cnt: number of entries in @sg
|
|
* @dir: %DMA_TO_DEVICE for RDMA WRITE, %DMA_FROM_DEVICE for RDMA READ
|
|
*/
|
|
void rdma_rw_ctx_destroy(struct rdma_rw_ctx *ctx, struct ib_qp *qp, u8 port_num,
|
|
struct scatterlist *sg, u32 sg_cnt, enum dma_data_direction dir)
|
|
{
|
|
int i;
|
|
|
|
switch (ctx->type) {
|
|
case RDMA_RW_MR:
|
|
for (i = 0; i < ctx->nr_ops; i++)
|
|
ib_mr_pool_put(qp, &qp->rdma_mrs, ctx->reg[i].mr);
|
|
kfree(ctx->reg);
|
|
break;
|
|
case RDMA_RW_MULTI_WR:
|
|
kfree(ctx->map.wrs);
|
|
kfree(ctx->map.sges);
|
|
break;
|
|
case RDMA_RW_SINGLE_WR:
|
|
break;
|
|
default:
|
|
BUG();
|
|
break;
|
|
}
|
|
|
|
/* P2PDMA contexts do not need to be unmapped */
|
|
if (!is_pci_p2pdma_page(sg_page(sg)))
|
|
ib_dma_unmap_sg(qp->pd->device, sg, sg_cnt, dir);
|
|
}
|
|
EXPORT_SYMBOL(rdma_rw_ctx_destroy);
|
|
|
|
/**
|
|
* rdma_rw_ctx_destroy_signature - release all resources allocated by
|
|
* rdma_rw_ctx_init_signature
|
|
* @ctx: context to release
|
|
* @qp: queue pair to operate on
|
|
* @port_num: port num to which the connection is bound
|
|
* @sg: scatterlist that was used for the READ/WRITE
|
|
* @sg_cnt: number of entries in @sg
|
|
* @prot_sg: scatterlist that was used for the READ/WRITE of the PI
|
|
* @prot_sg_cnt: number of entries in @prot_sg
|
|
* @dir: %DMA_TO_DEVICE for RDMA WRITE, %DMA_FROM_DEVICE for RDMA READ
|
|
*/
|
|
void rdma_rw_ctx_destroy_signature(struct rdma_rw_ctx *ctx, struct ib_qp *qp,
|
|
u8 port_num, struct scatterlist *sg, u32 sg_cnt,
|
|
struct scatterlist *prot_sg, u32 prot_sg_cnt,
|
|
enum dma_data_direction dir)
|
|
{
|
|
if (WARN_ON_ONCE(ctx->type != RDMA_RW_SIG_MR))
|
|
return;
|
|
|
|
ib_mr_pool_put(qp, &qp->rdma_mrs, ctx->sig->data.mr);
|
|
ib_dma_unmap_sg(qp->pd->device, sg, sg_cnt, dir);
|
|
|
|
if (ctx->sig->prot.mr) {
|
|
ib_mr_pool_put(qp, &qp->rdma_mrs, ctx->sig->prot.mr);
|
|
ib_dma_unmap_sg(qp->pd->device, prot_sg, prot_sg_cnt, dir);
|
|
}
|
|
|
|
ib_mr_pool_put(qp, &qp->sig_mrs, ctx->sig->sig_mr);
|
|
kfree(ctx->sig);
|
|
}
|
|
EXPORT_SYMBOL(rdma_rw_ctx_destroy_signature);
|
|
|
|
/**
|
|
* rdma_rw_mr_factor - return number of MRs required for a payload
|
|
* @device: device handling the connection
|
|
* @port_num: port num to which the connection is bound
|
|
* @maxpages: maximum payload pages per rdma_rw_ctx
|
|
*
|
|
* Returns the number of MRs the device requires to move @maxpayload
|
|
* bytes. The returned value is used during transport creation to
|
|
* compute max_rdma_ctxts and the size of the transport's Send and
|
|
* Send Completion Queues.
|
|
*/
|
|
unsigned int rdma_rw_mr_factor(struct ib_device *device, u8 port_num,
|
|
unsigned int maxpages)
|
|
{
|
|
unsigned int mr_pages;
|
|
|
|
if (rdma_rw_can_use_mr(device, port_num))
|
|
mr_pages = rdma_rw_fr_page_list_len(device);
|
|
else
|
|
mr_pages = device->attrs.max_sge_rd;
|
|
return DIV_ROUND_UP(maxpages, mr_pages);
|
|
}
|
|
EXPORT_SYMBOL(rdma_rw_mr_factor);
|
|
|
|
void rdma_rw_init_qp(struct ib_device *dev, struct ib_qp_init_attr *attr)
|
|
{
|
|
u32 factor;
|
|
|
|
WARN_ON_ONCE(attr->port_num == 0);
|
|
|
|
/*
|
|
* Each context needs at least one RDMA READ or WRITE WR.
|
|
*
|
|
* For some hardware we might need more, eventually we should ask the
|
|
* HCA driver for a multiplier here.
|
|
*/
|
|
factor = 1;
|
|
|
|
/*
|
|
* If the devices needs MRs to perform RDMA READ or WRITE operations,
|
|
* we'll need two additional MRs for the registrations and the
|
|
* invalidation.
|
|
*/
|
|
if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
|
|
factor += 6; /* (inv + reg) * (data + prot + sig) */
|
|
else if (rdma_rw_can_use_mr(dev, attr->port_num))
|
|
factor += 2; /* inv + reg */
|
|
|
|
attr->cap.max_send_wr += factor * attr->cap.max_rdma_ctxs;
|
|
|
|
/*
|
|
* But maybe we were just too high in the sky and the device doesn't
|
|
* even support all we need, and we'll have to live with what we get..
|
|
*/
|
|
attr->cap.max_send_wr =
|
|
min_t(u32, attr->cap.max_send_wr, dev->attrs.max_qp_wr);
|
|
}
|
|
|
|
int rdma_rw_init_mrs(struct ib_qp *qp, struct ib_qp_init_attr *attr)
|
|
{
|
|
struct ib_device *dev = qp->pd->device;
|
|
u32 nr_mrs = 0, nr_sig_mrs = 0;
|
|
int ret = 0;
|
|
|
|
if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN) {
|
|
nr_sig_mrs = attr->cap.max_rdma_ctxs;
|
|
nr_mrs = attr->cap.max_rdma_ctxs * 2;
|
|
} else if (rdma_rw_can_use_mr(dev, attr->port_num)) {
|
|
nr_mrs = attr->cap.max_rdma_ctxs;
|
|
}
|
|
|
|
if (nr_mrs) {
|
|
ret = ib_mr_pool_init(qp, &qp->rdma_mrs, nr_mrs,
|
|
IB_MR_TYPE_MEM_REG,
|
|
rdma_rw_fr_page_list_len(dev));
|
|
if (ret) {
|
|
pr_err("%s: failed to allocated %d MRs\n",
|
|
__func__, nr_mrs);
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
if (nr_sig_mrs) {
|
|
ret = ib_mr_pool_init(qp, &qp->sig_mrs, nr_sig_mrs,
|
|
IB_MR_TYPE_SIGNATURE, 2);
|
|
if (ret) {
|
|
pr_err("%s: failed to allocated %d SIG MRs\n",
|
|
__func__, nr_mrs);
|
|
goto out_free_rdma_mrs;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
|
|
out_free_rdma_mrs:
|
|
ib_mr_pool_destroy(qp, &qp->rdma_mrs);
|
|
return ret;
|
|
}
|
|
|
|
void rdma_rw_cleanup_mrs(struct ib_qp *qp)
|
|
{
|
|
ib_mr_pool_destroy(qp, &qp->sig_mrs);
|
|
ib_mr_pool_destroy(qp, &qp->rdma_mrs);
|
|
}
|