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The GPBR registers are used for storing RTC values. The GPBR registers to use are now provided using standard resource entry. The array is filled in SoC specific code. rtc-at91sam9 RTT as RTC driver is modified to retrieve this information. Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> [nicolas.ferre@atmel.com: rework resources assignment] Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Reviewed-by: Ryan Mallon <rmallon@gmail.com>
111 lines
3.8 KiB
C
111 lines
3.8 KiB
C
/*
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* arch/arm/mach-at91/include/mach/at91sam9260.h
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*
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* Copyright (C) 2007 Atmel Corporation
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*
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* Common definitions.
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* Based on AT91SAM9RL datasheet revision A. (Preliminary)
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive for
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* more details.
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*/
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#ifndef AT91SAM9RL_H
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#define AT91SAM9RL_H
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/*
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* Peripheral identifiers/interrupts.
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*/
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#define AT91SAM9RL_ID_PIOA 2 /* Parallel IO Controller A */
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#define AT91SAM9RL_ID_PIOB 3 /* Parallel IO Controller B */
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#define AT91SAM9RL_ID_PIOC 4 /* Parallel IO Controller C */
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#define AT91SAM9RL_ID_PIOD 5 /* Parallel IO Controller D */
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#define AT91SAM9RL_ID_US0 6 /* USART 0 */
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#define AT91SAM9RL_ID_US1 7 /* USART 1 */
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#define AT91SAM9RL_ID_US2 8 /* USART 2 */
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#define AT91SAM9RL_ID_US3 9 /* USART 3 */
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#define AT91SAM9RL_ID_MCI 10 /* Multimedia Card Interface */
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#define AT91SAM9RL_ID_TWI0 11 /* TWI 0 */
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#define AT91SAM9RL_ID_TWI1 12 /* TWI 1 */
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#define AT91SAM9RL_ID_SPI 13 /* Serial Peripheral Interface */
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#define AT91SAM9RL_ID_SSC0 14 /* Serial Synchronous Controller 0 */
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#define AT91SAM9RL_ID_SSC1 15 /* Serial Synchronous Controller 1 */
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#define AT91SAM9RL_ID_TC0 16 /* Timer Counter 0 */
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#define AT91SAM9RL_ID_TC1 17 /* Timer Counter 1 */
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#define AT91SAM9RL_ID_TC2 18 /* Timer Counter 2 */
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#define AT91SAM9RL_ID_PWMC 19 /* Pulse Width Modulation Controller */
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#define AT91SAM9RL_ID_TSC 20 /* Touch Screen Controller */
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#define AT91SAM9RL_ID_DMA 21 /* DMA Controller */
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#define AT91SAM9RL_ID_UDPHS 22 /* USB Device HS */
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#define AT91SAM9RL_ID_LCDC 23 /* LCD Controller */
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#define AT91SAM9RL_ID_AC97C 24 /* AC97 Controller */
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#define AT91SAM9RL_ID_IRQ0 31 /* Advanced Interrupt Controller (IRQ0) */
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/*
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* User Peripheral physical base addresses.
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*/
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#define AT91SAM9RL_BASE_TCB0 0xfffa0000
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#define AT91SAM9RL_BASE_TC0 0xfffa0000
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#define AT91SAM9RL_BASE_TC1 0xfffa0040
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#define AT91SAM9RL_BASE_TC2 0xfffa0080
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#define AT91SAM9RL_BASE_MCI 0xfffa4000
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#define AT91SAM9RL_BASE_TWI0 0xfffa8000
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#define AT91SAM9RL_BASE_TWI1 0xfffac000
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#define AT91SAM9RL_BASE_US0 0xfffb0000
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#define AT91SAM9RL_BASE_US1 0xfffb4000
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#define AT91SAM9RL_BASE_US2 0xfffb8000
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#define AT91SAM9RL_BASE_US3 0xfffbc000
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#define AT91SAM9RL_BASE_SSC0 0xfffc0000
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#define AT91SAM9RL_BASE_SSC1 0xfffc4000
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#define AT91SAM9RL_BASE_PWMC 0xfffc8000
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#define AT91SAM9RL_BASE_SPI 0xfffcc000
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#define AT91SAM9RL_BASE_TSC 0xfffd0000
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#define AT91SAM9RL_BASE_UDPHS 0xfffd4000
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#define AT91SAM9RL_BASE_AC97C 0xfffd8000
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/*
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* System Peripherals (offset from AT91_BASE_SYS)
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*/
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#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS)
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#define AT91SAM9RL_BASE_DMA 0xffffe600
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#define AT91SAM9RL_BASE_ECC 0xffffe800
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#define AT91SAM9RL_BASE_SDRAMC 0xffffea00
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#define AT91SAM9RL_BASE_SMC 0xffffec00
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#define AT91SAM9RL_BASE_MATRIX 0xffffee00
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#define AT91SAM9RL_BASE_DBGU AT91_BASE_DBGU0
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#define AT91SAM9RL_BASE_PIOA 0xfffff400
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#define AT91SAM9RL_BASE_PIOB 0xfffff600
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#define AT91SAM9RL_BASE_PIOC 0xfffff800
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#define AT91SAM9RL_BASE_PIOD 0xfffffa00
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#define AT91SAM9RL_BASE_RSTC 0xfffffd00
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#define AT91SAM9RL_BASE_SHDWC 0xfffffd10
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#define AT91SAM9RL_BASE_RTT 0xfffffd20
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#define AT91SAM9RL_BASE_PIT 0xfffffd30
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#define AT91SAM9RL_BASE_WDT 0xfffffd40
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#define AT91SAM9RL_BASE_GPBR 0xfffffd60
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#define AT91SAM9RL_BASE_RTC 0xfffffe00
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#define AT91_USART0 AT91SAM9RL_BASE_US0
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#define AT91_USART1 AT91SAM9RL_BASE_US1
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#define AT91_USART2 AT91SAM9RL_BASE_US2
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#define AT91_USART3 AT91SAM9RL_BASE_US3
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/*
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* Internal Memory.
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*/
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#define AT91SAM9RL_SRAM_BASE 0x00300000 /* Internal SRAM base address */
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#define AT91SAM9RL_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */
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#define AT91SAM9RL_ROM_BASE 0x00400000 /* Internal ROM base address */
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#define AT91SAM9RL_ROM_SIZE (2 * SZ_16K) /* Internal ROM size (32Kb) */
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#define AT91SAM9RL_LCDC_BASE 0x00500000 /* LCD Controller */
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#define AT91SAM9RL_UDPHS_FIFO 0x00600000 /* USB Device HS controller */
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#endif
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