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8d8ccdd2e6
This reverts commit b804923b7c.
Due to the compatible changing of mt8195 from "mediatek,mt8195-mmsys"
to "mediatek,mt8195-vdosys0", we have to revert this patch and send a
new patch with the new compatible.
Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
Link: https://lore.kernel.org/r/20220927152704.12018-3-jason-jh.lin@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
274 lines
8.3 KiB
C
274 lines
8.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __SOC_MEDIATEK_MTK_MMSYS_H
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#define __SOC_MEDIATEK_MTK_MMSYS_H
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#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
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#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044
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#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048
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#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
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#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050
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#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
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#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
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#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4
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#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8
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#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
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#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8
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#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
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#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
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#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
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#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
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#define DISP_REG_CONFIG_OUT_SEL 0x04c
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#define DISP_REG_CONFIG_DSI_SEL 0x050
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#define DISP_REG_CONFIG_DPI_SEL 0x064
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#define OVL0_MOUT_EN_COLOR0 0x1
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#define OD_MOUT_EN_RDMA0 0x1
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#define OD1_MOUT_EN_RDMA1 BIT(16)
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#define UFOE_MOUT_EN_DSI0 0x1
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#define COLOR0_SEL_IN_OVL0 0x1
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#define OVL1_MOUT_EN_COLOR1 0x1
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#define GAMMA_MOUT_EN_RDMA1 0x1
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#define RDMA0_SOUT_DPI0 0x2
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#define RDMA0_SOUT_DPI1 0x3
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#define RDMA0_SOUT_DSI1 0x1
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#define RDMA0_SOUT_DSI2 0x4
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#define RDMA0_SOUT_DSI3 0x5
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#define RDMA0_SOUT_MASK 0x7
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#define RDMA1_SOUT_DPI0 0x2
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#define RDMA1_SOUT_DPI1 0x3
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#define RDMA1_SOUT_DSI1 0x1
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#define RDMA1_SOUT_DSI2 0x4
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#define RDMA1_SOUT_DSI3 0x5
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#define RDMA1_SOUT_MASK 0x7
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#define RDMA2_SOUT_DPI0 0x2
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#define RDMA2_SOUT_DPI1 0x3
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#define RDMA2_SOUT_DSI1 0x1
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#define RDMA2_SOUT_DSI2 0x4
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#define RDMA2_SOUT_DSI3 0x5
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#define RDMA2_SOUT_MASK 0x7
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#define DPI0_SEL_IN_RDMA1 0x1
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#define DPI0_SEL_IN_RDMA2 0x3
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#define DPI0_SEL_IN_MASK 0x3
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#define DPI1_SEL_IN_RDMA1 (0x1 << 8)
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#define DPI1_SEL_IN_RDMA2 (0x3 << 8)
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#define DPI1_SEL_IN_MASK (0x3 << 8)
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#define DSI0_SEL_IN_RDMA1 0x1
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#define DSI0_SEL_IN_RDMA2 0x4
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#define DSI0_SEL_IN_MASK 0x7
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#define DSI1_SEL_IN_RDMA1 0x1
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#define DSI1_SEL_IN_RDMA2 0x4
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#define DSI1_SEL_IN_MASK 0x7
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#define DSI2_SEL_IN_RDMA1 (0x1 << 16)
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#define DSI2_SEL_IN_RDMA2 (0x4 << 16)
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#define DSI2_SEL_IN_MASK (0x7 << 16)
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#define DSI3_SEL_IN_RDMA1 (0x1 << 16)
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#define DSI3_SEL_IN_RDMA2 (0x4 << 16)
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#define DSI3_SEL_IN_MASK (0x7 << 16)
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#define COLOR1_SEL_IN_OVL1 0x1
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#define OVL_MOUT_EN_RDMA 0x1
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#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8
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#define BLS_TO_DPI_RDMA1_TO_DSI 0x2
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#define BLS_RDMA1_DSI_DPI_MASK 0xf
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#define DSI_SEL_IN_BLS 0x0
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#define DPI_SEL_IN_BLS 0x0
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#define DPI_SEL_IN_MASK 0x1
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#define DSI_SEL_IN_RDMA 0x1
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#define DSI_SEL_IN_MASK 0x1
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struct mtk_mmsys_routes {
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u32 from_comp;
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u32 to_comp;
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u32 addr;
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u32 mask;
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u32 val;
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};
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struct mtk_mmsys_driver_data {
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const char *clk_driver;
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const struct mtk_mmsys_routes *routes;
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const unsigned int num_routes;
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const u16 sw0_rst_offset;
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};
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/*
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* Routes in mt8173, mt2701, mt2712 are different. That means
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* in the same register address, it controls different input/output
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* selection for each SoC. But, right now, they use the same table as
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* default routes meet their requirements. But we don't have the complete
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* route information for these three SoC, so just keep them in the same
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* table. After we've more information, we could separate mt2701, mt2712
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* to an independent table.
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*/
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static const struct mtk_mmsys_routes mmsys_default_routing_table[] = {
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{
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DDP_COMPONENT_BLS, DDP_COMPONENT_DSI0,
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DISP_REG_CONFIG_OUT_SEL, BLS_RDMA1_DSI_DPI_MASK,
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BLS_TO_DSI_RDMA1_TO_DPI1
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}, {
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DDP_COMPONENT_BLS, DDP_COMPONENT_DSI0,
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DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_MASK,
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DSI_SEL_IN_BLS
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}, {
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DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,
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DISP_REG_CONFIG_OUT_SEL, BLS_RDMA1_DSI_DPI_MASK,
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BLS_TO_DPI_RDMA1_TO_DSI
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}, {
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DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,
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DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_MASK,
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DSI_SEL_IN_RDMA
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}, {
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DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,
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DISP_REG_CONFIG_DPI_SEL, DPI_SEL_IN_MASK,
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DPI_SEL_IN_BLS
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}, {
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DDP_COMPONENT_GAMMA, DDP_COMPONENT_RDMA1,
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DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN, GAMMA_MOUT_EN_RDMA1,
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GAMMA_MOUT_EN_RDMA1
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}, {
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DDP_COMPONENT_OD0, DDP_COMPONENT_RDMA0,
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DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD_MOUT_EN_RDMA0,
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OD_MOUT_EN_RDMA0
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}, {
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DDP_COMPONENT_OD1, DDP_COMPONENT_RDMA1,
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DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD1_MOUT_EN_RDMA1,
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OD1_MOUT_EN_RDMA1
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}, {
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DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
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DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,
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OVL0_MOUT_EN_COLOR0
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}, {
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DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
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DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0,
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COLOR0_SEL_IN_OVL0
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}, {
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DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
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DISP_REG_CONFIG_DISP_OVL_MOUT_EN, OVL_MOUT_EN_RDMA,
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OVL_MOUT_EN_RDMA
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}, {
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DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1,
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DISP_REG_CONFIG_DISP_OVL1_MOUT_EN, OVL1_MOUT_EN_COLOR1,
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OVL1_MOUT_EN_COLOR1
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}, {
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DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1,
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DISP_REG_CONFIG_DISP_COLOR1_SEL_IN, COLOR1_SEL_IN_OVL1,
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COLOR1_SEL_IN_OVL1
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}, {
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DDP_COMPONENT_RDMA0, DDP_COMPONENT_DPI0,
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DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
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RDMA0_SOUT_DPI0
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}, {
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DDP_COMPONENT_RDMA0, DDP_COMPONENT_DPI1,
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DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
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RDMA0_SOUT_DPI1
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}, {
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DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI1,
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DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
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RDMA0_SOUT_DSI1
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}, {
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DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI2,
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DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
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RDMA0_SOUT_DSI2
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}, {
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DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI3,
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DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
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RDMA0_SOUT_DSI3
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}, {
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DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
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DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
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RDMA1_SOUT_DPI0
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}, {
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DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
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DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_MASK,
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DPI0_SEL_IN_RDMA1
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}, {
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DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI1,
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DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
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RDMA1_SOUT_DPI1
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}, {
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DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI1,
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DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_MASK,
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DPI1_SEL_IN_RDMA1
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}, {
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DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI0,
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DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_MASK,
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DSI0_SEL_IN_RDMA1
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}, {
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DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI1,
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DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
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RDMA1_SOUT_DSI1
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}, {
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DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI1,
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DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_MASK,
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DSI1_SEL_IN_RDMA1
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}, {
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DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI2,
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DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
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RDMA1_SOUT_DSI2
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}, {
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DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI2,
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DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_MASK,
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DSI2_SEL_IN_RDMA1
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}, {
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DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI3,
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DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
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RDMA1_SOUT_DSI3
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}, {
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DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI3,
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DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_MASK,
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DSI3_SEL_IN_RDMA1
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}, {
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DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI0,
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DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
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RDMA2_SOUT_DPI0
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}, {
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DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI0,
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DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_MASK,
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DPI0_SEL_IN_RDMA2
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}, {
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DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI1,
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DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
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RDMA2_SOUT_DPI1
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}, {
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DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI1,
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DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_MASK,
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DPI1_SEL_IN_RDMA2
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}, {
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DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI0,
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DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_MASK,
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DSI0_SEL_IN_RDMA2
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}, {
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DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI1,
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DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
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RDMA2_SOUT_DSI1
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}, {
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DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI1,
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DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_MASK,
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DSI1_SEL_IN_RDMA2
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}, {
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DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI2,
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DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
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RDMA2_SOUT_DSI2
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}, {
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DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI2,
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DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_MASK,
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DSI2_SEL_IN_RDMA2
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}, {
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DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI3,
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DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
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RDMA2_SOUT_DSI3
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}, {
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DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI3,
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DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_MASK,
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DSI3_SEL_IN_RDMA2
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}, {
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DDP_COMPONENT_UFOE, DDP_COMPONENT_DSI0,
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DISP_REG_CONFIG_DISP_UFOE_MOUT_EN, UFOE_MOUT_EN_DSI0,
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UFOE_MOUT_EN_DSI0
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}
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};
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#endif /* __SOC_MEDIATEK_MTK_MMSYS_H */
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