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1745522ccb
Signed-off-by: Jean Delvare <khali@linux-fr.org>
655 lines
14 KiB
C
655 lines
14 KiB
C
/*
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Copyright (c) 2001,2002 Christer Weinigel <wingel@nano-system.com>
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National Semiconductor SCx200 ACCESS.bus support
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Also supports the AMD CS5535 and AMD CS5536
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Based on i2c-keywest.c which is:
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Copyright (c) 2001 Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Copyright (c) 2000 Philip Edelbrock <phil@stimpy.netroedge.com>
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation; either version 2 of the
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License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/module.h>
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/i2c.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/mutex.h>
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#include <asm/io.h>
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#include <linux/scx200.h>
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#define NAME "scx200_acb"
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MODULE_AUTHOR("Christer Weinigel <wingel@nano-system.com>");
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MODULE_DESCRIPTION("NatSemi SCx200 ACCESS.bus Driver");
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MODULE_LICENSE("GPL");
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#define MAX_DEVICES 4
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static int base[MAX_DEVICES] = { 0x820, 0x840 };
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module_param_array(base, int, NULL, 0);
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MODULE_PARM_DESC(base, "Base addresses for the ACCESS.bus controllers");
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#define POLL_TIMEOUT (HZ/5)
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enum scx200_acb_state {
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state_idle,
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state_address,
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state_command,
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state_repeat_start,
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state_quick,
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state_read,
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state_write,
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};
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static const char *scx200_acb_state_name[] = {
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"idle",
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"address",
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"command",
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"repeat_start",
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"quick",
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"read",
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"write",
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};
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/* Physical interface */
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struct scx200_acb_iface {
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struct scx200_acb_iface *next;
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struct i2c_adapter adapter;
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unsigned base;
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struct mutex mutex;
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/* State machine data */
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enum scx200_acb_state state;
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int result;
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u8 address_byte;
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u8 command;
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u8 *ptr;
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char needs_reset;
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unsigned len;
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/* PCI device info */
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struct pci_dev *pdev;
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int bar;
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};
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/* Register Definitions */
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#define ACBSDA (iface->base + 0)
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#define ACBST (iface->base + 1)
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#define ACBST_SDAST 0x40 /* SDA Status */
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#define ACBST_BER 0x20
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#define ACBST_NEGACK 0x10 /* Negative Acknowledge */
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#define ACBST_STASTR 0x08 /* Stall After Start */
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#define ACBST_MASTER 0x02
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#define ACBCST (iface->base + 2)
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#define ACBCST_BB 0x02
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#define ACBCTL1 (iface->base + 3)
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#define ACBCTL1_STASTRE 0x80
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#define ACBCTL1_NMINTE 0x40
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#define ACBCTL1_ACK 0x10
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#define ACBCTL1_STOP 0x02
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#define ACBCTL1_START 0x01
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#define ACBADDR (iface->base + 4)
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#define ACBCTL2 (iface->base + 5)
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#define ACBCTL2_ENABLE 0x01
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/************************************************************************/
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static void scx200_acb_machine(struct scx200_acb_iface *iface, u8 status)
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{
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const char *errmsg;
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dev_dbg(&iface->adapter.dev, "state %s, status = 0x%02x\n",
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scx200_acb_state_name[iface->state], status);
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if (status & ACBST_BER) {
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errmsg = "bus error";
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goto error;
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}
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if (!(status & ACBST_MASTER)) {
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errmsg = "not master";
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goto error;
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}
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if (status & ACBST_NEGACK) {
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dev_dbg(&iface->adapter.dev, "negative ack in state %s\n",
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scx200_acb_state_name[iface->state]);
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iface->state = state_idle;
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iface->result = -ENXIO;
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outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1);
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outb(ACBST_STASTR | ACBST_NEGACK, ACBST);
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/* Reset the status register */
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outb(0, ACBST);
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return;
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}
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switch (iface->state) {
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case state_idle:
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dev_warn(&iface->adapter.dev, "interrupt in idle state\n");
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break;
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case state_address:
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/* Do a pointer write first */
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outb(iface->address_byte & ~1, ACBSDA);
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iface->state = state_command;
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break;
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case state_command:
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outb(iface->command, ACBSDA);
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if (iface->address_byte & 1)
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iface->state = state_repeat_start;
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else
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iface->state = state_write;
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break;
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case state_repeat_start:
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outb(inb(ACBCTL1) | ACBCTL1_START, ACBCTL1);
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/* fallthrough */
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case state_quick:
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if (iface->address_byte & 1) {
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if (iface->len == 1)
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outb(inb(ACBCTL1) | ACBCTL1_ACK, ACBCTL1);
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else
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outb(inb(ACBCTL1) & ~ACBCTL1_ACK, ACBCTL1);
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outb(iface->address_byte, ACBSDA);
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iface->state = state_read;
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} else {
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outb(iface->address_byte, ACBSDA);
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iface->state = state_write;
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}
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break;
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case state_read:
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/* Set ACK if _next_ byte will be the last one */
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if (iface->len == 2)
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outb(inb(ACBCTL1) | ACBCTL1_ACK, ACBCTL1);
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else
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outb(inb(ACBCTL1) & ~ACBCTL1_ACK, ACBCTL1);
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if (iface->len == 1) {
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iface->result = 0;
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iface->state = state_idle;
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outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1);
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}
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*iface->ptr++ = inb(ACBSDA);
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--iface->len;
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break;
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case state_write:
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if (iface->len == 0) {
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iface->result = 0;
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iface->state = state_idle;
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outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1);
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break;
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}
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outb(*iface->ptr++, ACBSDA);
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--iface->len;
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break;
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}
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return;
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error:
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dev_err(&iface->adapter.dev, "%s in state %s\n", errmsg,
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scx200_acb_state_name[iface->state]);
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iface->state = state_idle;
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iface->result = -EIO;
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iface->needs_reset = 1;
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}
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static void scx200_acb_poll(struct scx200_acb_iface *iface)
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{
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u8 status;
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unsigned long timeout;
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timeout = jiffies + POLL_TIMEOUT;
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while (1) {
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status = inb(ACBST);
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/* Reset the status register to avoid the hang */
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outb(0, ACBST);
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if ((status & (ACBST_SDAST|ACBST_BER|ACBST_NEGACK)) != 0) {
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scx200_acb_machine(iface, status);
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return;
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}
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if (time_after(jiffies, timeout))
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break;
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cpu_relax();
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cond_resched();
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}
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dev_err(&iface->adapter.dev, "timeout in state %s\n",
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scx200_acb_state_name[iface->state]);
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iface->state = state_idle;
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iface->result = -EIO;
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iface->needs_reset = 1;
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}
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static void scx200_acb_reset(struct scx200_acb_iface *iface)
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{
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/* Disable the ACCESS.bus device and Configure the SCL
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frequency: 16 clock cycles */
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outb(0x70, ACBCTL2);
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/* Polling mode */
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outb(0, ACBCTL1);
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/* Disable slave address */
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outb(0, ACBADDR);
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/* Enable the ACCESS.bus device */
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outb(inb(ACBCTL2) | ACBCTL2_ENABLE, ACBCTL2);
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/* Free STALL after START */
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outb(inb(ACBCTL1) & ~(ACBCTL1_STASTRE | ACBCTL1_NMINTE), ACBCTL1);
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/* Send a STOP */
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outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1);
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/* Clear BER, NEGACK and STASTR bits */
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outb(ACBST_BER | ACBST_NEGACK | ACBST_STASTR, ACBST);
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/* Clear BB bit */
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outb(inb(ACBCST) | ACBCST_BB, ACBCST);
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}
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static s32 scx200_acb_smbus_xfer(struct i2c_adapter *adapter,
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u16 address, unsigned short flags,
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char rw, u8 command, int size,
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union i2c_smbus_data *data)
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{
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struct scx200_acb_iface *iface = i2c_get_adapdata(adapter);
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int len;
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u8 *buffer;
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u16 cur_word;
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int rc;
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switch (size) {
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case I2C_SMBUS_QUICK:
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len = 0;
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buffer = NULL;
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break;
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case I2C_SMBUS_BYTE:
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len = 1;
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buffer = rw ? &data->byte : &command;
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break;
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case I2C_SMBUS_BYTE_DATA:
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len = 1;
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buffer = &data->byte;
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break;
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case I2C_SMBUS_WORD_DATA:
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len = 2;
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cur_word = cpu_to_le16(data->word);
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buffer = (u8 *)&cur_word;
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break;
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case I2C_SMBUS_I2C_BLOCK_DATA:
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len = data->block[0];
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if (len == 0 || len > I2C_SMBUS_BLOCK_MAX)
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return -EINVAL;
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buffer = &data->block[1];
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break;
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default:
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return -EINVAL;
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}
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dev_dbg(&adapter->dev,
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"size=%d, address=0x%x, command=0x%x, len=%d, read=%d\n",
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size, address, command, len, rw);
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if (!len && rw == I2C_SMBUS_READ) {
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dev_dbg(&adapter->dev, "zero length read\n");
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return -EINVAL;
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}
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mutex_lock(&iface->mutex);
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iface->address_byte = (address << 1) | rw;
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iface->command = command;
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iface->ptr = buffer;
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iface->len = len;
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iface->result = -EINVAL;
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iface->needs_reset = 0;
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outb(inb(ACBCTL1) | ACBCTL1_START, ACBCTL1);
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if (size == I2C_SMBUS_QUICK || size == I2C_SMBUS_BYTE)
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iface->state = state_quick;
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else
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iface->state = state_address;
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while (iface->state != state_idle)
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scx200_acb_poll(iface);
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if (iface->needs_reset)
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scx200_acb_reset(iface);
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rc = iface->result;
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mutex_unlock(&iface->mutex);
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if (rc == 0 && size == I2C_SMBUS_WORD_DATA && rw == I2C_SMBUS_READ)
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data->word = le16_to_cpu(cur_word);
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#ifdef DEBUG
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dev_dbg(&adapter->dev, "transfer done, result: %d", rc);
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if (buffer) {
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int i;
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printk(" data:");
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for (i = 0; i < len; ++i)
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printk(" %02x", buffer[i]);
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}
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printk("\n");
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#endif
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return rc;
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}
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static u32 scx200_acb_func(struct i2c_adapter *adapter)
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{
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return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
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I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
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I2C_FUNC_SMBUS_I2C_BLOCK;
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}
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/* For now, we only handle combined mode (smbus) */
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static const struct i2c_algorithm scx200_acb_algorithm = {
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.smbus_xfer = scx200_acb_smbus_xfer,
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.functionality = scx200_acb_func,
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};
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static struct scx200_acb_iface *scx200_acb_list;
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static DEFINE_MUTEX(scx200_acb_list_mutex);
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static __init int scx200_acb_probe(struct scx200_acb_iface *iface)
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{
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u8 val;
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/* Disable the ACCESS.bus device and Configure the SCL
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frequency: 16 clock cycles */
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outb(0x70, ACBCTL2);
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if (inb(ACBCTL2) != 0x70) {
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pr_debug(NAME ": ACBCTL2 readback failed\n");
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return -ENXIO;
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}
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outb(inb(ACBCTL1) | ACBCTL1_NMINTE, ACBCTL1);
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val = inb(ACBCTL1);
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if (val) {
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pr_debug(NAME ": disabled, but ACBCTL1=0x%02x\n",
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val);
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return -ENXIO;
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}
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outb(inb(ACBCTL2) | ACBCTL2_ENABLE, ACBCTL2);
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outb(inb(ACBCTL1) | ACBCTL1_NMINTE, ACBCTL1);
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val = inb(ACBCTL1);
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if ((val & ACBCTL1_NMINTE) != ACBCTL1_NMINTE) {
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pr_debug(NAME ": enabled, but NMINTE won't be set, "
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"ACBCTL1=0x%02x\n", val);
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return -ENXIO;
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}
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return 0;
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}
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static __init struct scx200_acb_iface *scx200_create_iface(const char *text,
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struct device *dev, int index)
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{
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struct scx200_acb_iface *iface;
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struct i2c_adapter *adapter;
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iface = kzalloc(sizeof(*iface), GFP_KERNEL);
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if (!iface) {
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printk(KERN_ERR NAME ": can't allocate memory\n");
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return NULL;
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}
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adapter = &iface->adapter;
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i2c_set_adapdata(adapter, iface);
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snprintf(adapter->name, sizeof(adapter->name), "%s ACB%d", text, index);
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adapter->owner = THIS_MODULE;
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adapter->algo = &scx200_acb_algorithm;
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adapter->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
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adapter->dev.parent = dev;
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mutex_init(&iface->mutex);
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return iface;
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}
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static int __init scx200_acb_create(struct scx200_acb_iface *iface)
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{
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struct i2c_adapter *adapter;
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int rc;
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adapter = &iface->adapter;
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rc = scx200_acb_probe(iface);
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if (rc) {
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printk(KERN_WARNING NAME ": probe failed\n");
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return rc;
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}
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scx200_acb_reset(iface);
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if (i2c_add_adapter(adapter) < 0) {
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printk(KERN_ERR NAME ": failed to register\n");
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return -ENODEV;
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}
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mutex_lock(&scx200_acb_list_mutex);
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iface->next = scx200_acb_list;
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scx200_acb_list = iface;
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mutex_unlock(&scx200_acb_list_mutex);
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return 0;
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}
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static __init int scx200_create_pci(const char *text, struct pci_dev *pdev,
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int bar)
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{
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struct scx200_acb_iface *iface;
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int rc;
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iface = scx200_create_iface(text, &pdev->dev, 0);
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if (iface == NULL)
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return -ENOMEM;
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iface->pdev = pdev;
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iface->bar = bar;
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rc = pci_enable_device_io(iface->pdev);
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if (rc)
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goto errout_free;
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rc = pci_request_region(iface->pdev, iface->bar, iface->adapter.name);
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if (rc) {
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printk(KERN_ERR NAME ": can't allocate PCI BAR %d\n",
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iface->bar);
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goto errout_free;
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}
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iface->base = pci_resource_start(iface->pdev, iface->bar);
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rc = scx200_acb_create(iface);
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if (rc == 0)
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return 0;
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pci_release_region(iface->pdev, iface->bar);
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pci_dev_put(iface->pdev);
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errout_free:
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kfree(iface);
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return rc;
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}
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static int __init scx200_create_isa(const char *text, unsigned long base,
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int index)
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{
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struct scx200_acb_iface *iface;
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int rc;
|
|
|
|
iface = scx200_create_iface(text, NULL, index);
|
|
|
|
if (iface == NULL)
|
|
return -ENOMEM;
|
|
|
|
if (!request_region(base, 8, iface->adapter.name)) {
|
|
printk(KERN_ERR NAME ": can't allocate io 0x%lx-0x%lx\n",
|
|
base, base + 8 - 1);
|
|
rc = -EBUSY;
|
|
goto errout_free;
|
|
}
|
|
|
|
iface->base = base;
|
|
rc = scx200_acb_create(iface);
|
|
|
|
if (rc == 0)
|
|
return 0;
|
|
|
|
release_region(base, 8);
|
|
errout_free:
|
|
kfree(iface);
|
|
return rc;
|
|
}
|
|
|
|
/* Driver data is an index into the scx200_data array that indicates
|
|
* the name and the BAR where the I/O address resource is located. ISA
|
|
* devices are flagged with a bar value of -1 */
|
|
|
|
static struct pci_device_id scx200_pci[] = {
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SCx200_BRIDGE),
|
|
.driver_data = 0 },
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SC1100_BRIDGE),
|
|
.driver_data = 0 },
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_CS5535_ISA),
|
|
.driver_data = 1 },
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA),
|
|
.driver_data = 2 }
|
|
};
|
|
|
|
static struct {
|
|
const char *name;
|
|
int bar;
|
|
} scx200_data[] = {
|
|
{ "SCx200", -1 },
|
|
{ "CS5535", 0 },
|
|
{ "CS5536", 0 }
|
|
};
|
|
|
|
static __init int scx200_scan_pci(void)
|
|
{
|
|
int data, dev;
|
|
int rc = -ENODEV;
|
|
struct pci_dev *pdev;
|
|
|
|
for(dev = 0; dev < ARRAY_SIZE(scx200_pci); dev++) {
|
|
pdev = pci_get_device(scx200_pci[dev].vendor,
|
|
scx200_pci[dev].device, NULL);
|
|
|
|
if (pdev == NULL)
|
|
continue;
|
|
|
|
data = scx200_pci[dev].driver_data;
|
|
|
|
/* if .bar is greater or equal to zero, this is a
|
|
* PCI device - otherwise, we assume
|
|
that the ports are ISA based
|
|
*/
|
|
|
|
if (scx200_data[data].bar >= 0)
|
|
rc = scx200_create_pci(scx200_data[data].name, pdev,
|
|
scx200_data[data].bar);
|
|
else {
|
|
int i;
|
|
|
|
pci_dev_put(pdev);
|
|
for (i = 0; i < MAX_DEVICES; ++i) {
|
|
if (base[i] == 0)
|
|
continue;
|
|
|
|
rc = scx200_create_isa(scx200_data[data].name,
|
|
base[i],
|
|
i);
|
|
}
|
|
}
|
|
|
|
break;
|
|
}
|
|
|
|
return rc;
|
|
}
|
|
|
|
static int __init scx200_acb_init(void)
|
|
{
|
|
int rc;
|
|
|
|
pr_debug(NAME ": NatSemi SCx200 ACCESS.bus Driver\n");
|
|
|
|
rc = scx200_scan_pci();
|
|
|
|
/* If at least one bus was created, init must succeed */
|
|
if (scx200_acb_list)
|
|
return 0;
|
|
return rc;
|
|
}
|
|
|
|
static void __exit scx200_acb_cleanup(void)
|
|
{
|
|
struct scx200_acb_iface *iface;
|
|
|
|
mutex_lock(&scx200_acb_list_mutex);
|
|
while ((iface = scx200_acb_list) != NULL) {
|
|
scx200_acb_list = iface->next;
|
|
mutex_unlock(&scx200_acb_list_mutex);
|
|
|
|
i2c_del_adapter(&iface->adapter);
|
|
|
|
if (iface->pdev) {
|
|
pci_release_region(iface->pdev, iface->bar);
|
|
pci_dev_put(iface->pdev);
|
|
}
|
|
else
|
|
release_region(iface->base, 8);
|
|
|
|
kfree(iface);
|
|
mutex_lock(&scx200_acb_list_mutex);
|
|
}
|
|
mutex_unlock(&scx200_acb_list_mutex);
|
|
}
|
|
|
|
module_init(scx200_acb_init);
|
|
module_exit(scx200_acb_cleanup);
|